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Max cavity size and max cavity component count were offered as reports in the 16.5 release and are now available as DRCs in the 16.6 release of Allegro PCB Editor. Fab houses supporting embedded component manufacturing offer design guidelines on cavity usage. 

Consider a PCB with the following characteristics. Layer SIGNAL_7 is displayed where you see two merged cavities on the left as the result of Cap placement combined…

In this week's Whiteboard Wednesdays video, Lou Ternullo takes a closer look at what to consider when you are considering specialty memories, such as Wide I/O, HBM, and HMC.

https://youtu.be/vJi13D8mNSI

You still have a chance to get a paper accepted at the premier conference for memory technology—MemCon 2015.

Yes, on Tuesday, October 13, 2015, the brightest minds in memory technology will meet again at the Santa Clara Convention Center. The call for papers closes Friday, so it’s time to think about how you can further your career and showcase your understanding of key memory technologies.

See the full…

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to Z).
For this purpose, the e language defines the mvl type – a predefined enumerated type, with values of MVL_U, MVL_X, MVL_0, MVL_1, MVL_Z, MVL_W, MVL_L, MVL_H, and MVL_N (based on the VHDL std_logic type).

If you need…

The art of expressing hardware functionality through constraint language is often one of the trickiest parts of functional verification. Unlike procedural actions that are executed locally one by one, constraints are scattered declarative entities that define the rules for the gen actions. Therefore you don't necessarily see clearly how constraints are impacting the generation. This situation opens the door for occasional…

Hi Everyone,

Last time we got a quick look at The Innovus Standard Flow. Now I'd like to show you a bit more detail about some of the major steps. One of the new concepts in Innovus is how placement and pre-CTS timing optimization are now combined and interleaved. The GigaPlace placement engine is also new, and you will learn about its features. Click below to play the video (you'll need an active support.cadence.com…

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how Address Translation Services is implemented in a system.

https://youtu.be/yOSALM5X1ZM

The PCI-SIG Developers Conference happening today and tomorrow will be yet another exciting PCI-SIG event that Cadence is proud to participate in. We’ve been attending and showcasing technology at these conferences for many years now, sharing news and insights about our verification IP, controllers, and PHY solutions.

Cadence was the first commercial PCI Express 3.0 IP provider, and has continued that tradition…

There is a team at Cadence working on developing the next generation of Cadence documentation and Help interface.  After rolling your eyes at this statement, I'd really like you to take 10 minutes to complete our brief (honest) survey to help us improve our documentation delivery in the future. 

Here's the link: Cadence Documentation Survey

And in case you haven't looked under the Help menu in your Virtuoso window…

When I think back back just a few years ago, there were only a handful of devices that noticeably responded to changes in their environment by sensing the presence of something or a change in position. Not that these were the only ones, but these were the ones that were part of my regular “consumer” interaction with the world in my daily life:

• Tilt sensors in game controllers then in tablets and smart…

In this week's Whiteboard Wednesday video, William Chen explains the many benefits of designing your SoC using a multi-protocol PHY.

https://youtu.be/_W4BRr1RL_Y

Cadence’s Tensilica team was honored with the Best Paper Award at the IP track at the Design Automation Conference last week for “Design in the Eye of the Hurricane—Building Optimal Vision Processing Systems.” The paper highlighted the technology behind the Tensilica IVP (Image/Vision Processing) DSP.

Cadence IP Group CTO Chris Rowen accepted the award (pictured) on behalf of the team which included…

1. Cadence Documentation Survey

Cadence is committed to providing high-quality documentation. To help us shape the future of Cadence documentation delivery, we welcome you to complete our survey.

2. Virtuoso Spectre Transient Noise Analysis

This document discusses the theoretical background of the Spectre solution’s transient noise analysis, its implementation and implications…

So you've looked at Google project ARA and you have the most brilliant idea for a module that would be the hardware answer to Angry Birds, you take the next step and download the Module Developers Kits (MDK), and then you realize that the platform is based on MIPI UniPro Switch. That's the first time your confidence is damaged as there is no other platform out there that is based on UniPro switch. When taking a deeper…

Many times a user would like to be able to modify the behavior of a program based on arguments on the command line. Let’s take as an example a user who would like to pass the name of a file which includes input parameters to the e program.

In the C language this can be done using argv, which is an array of strings where each array element represents a command line argument. However, since Specman and the simulator…

In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. 

This environment is functional—exercising the DUT interfaces containing one system-level checker—but something is flawed in this picture. We have UVCs instantiated side by side, rather than in their “natural” location in the hierarchy. In a UVM…

Hi Everyone,

Last week I highlighted a video featuring Innovus User Interface Tips. Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should start with what's called the Standard Flow. There is a great document on support.cadence.com outlining this flow. I found it very interesting, and I can't wait to try it on my next design. You'll need an active support…

In the previous blog post, we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e.

In this post, we will show a fast way for adding a system-level data checker – using the UVM Scoreboard.  The UVM Scoreboard is an open-source framework, implemented in e, and is released as part of the UVM e Library. 

For adding a scoreboard to our XSerial-to-UBus environment, we define…

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion gates and it’s time to modernize VCD. If you stop by the Verification Academy booth at DAC on Tuesday June 9 at 5pm, you’ll learn how.

Now that I’ve piqued your interest, lets take a look at why…

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica configurable processors and what is involved in using them.

https://youtu.be/5rnQyoTLVvY