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If it wasn’t for the fact that USB has always been spelled with capital letters, I would say that with the introduction of USB Type-C the organization behind all things USB—USB Implementers Forum—has truly earned for USB to be spelled with a capital letter (U stands for Universal). Maybe it should be also bold now?

We’re inviting you to view the second part of the interview Jeff Ravencraft, the President…

Starting Dec. 5^th, 11 PSATRI members attended a five-day workshop on the Cadence Virtuoso front-to-back flow. PSATRI stands for Prince Sultan Advanced Technology Research Institute, which is part of the King Saud University in Riad, Saudi Arabia. Attendees...

In case you don’t know, USB Implementers Forum (USB-IF, for short) is the organization behind all things USB. Its president and COO, Jeff Ravencraft, sat down in the Cadence video studio and answered our questions about the role of USB-IF in the industry and what’s cooking for the USB implementers and users.

With so many new possibilities that are opening for USB developers, Jeff did his best to keep it short…

Neils Bohr, the physicist (or should that be the quantum mechanic) famously said "Prediction is very difficult, especially about the future." The semiconductor industry, despite its incredible complexity, is easier to predict than many other industries...

So the lede is that Chris Rowen has been elected an IEEE Fellow. In a sense it is actually a group award, because he couldn't have achieved what he has without the teams that surrounded him, in most cases teams for which he assembled the key players himself...

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the inter-workings of neural networks, which are applied to a variety of data types for pattern recognition. Hear Chris explain what is happening computationally in the functioning of a neural network.

https://youtu.be/HfmJIsZY00o

The 16.6-2015 Allegro Design Workbench (ADW) release contains a significant enhancement that allows traditional Project Manager-based designs to use the same database enabled Component Browser used in ADW projects. Yes, the Component Browser can read the ADW database when editing projects in a Project Manager (non-ADW) flow.

Some designers want to stay in a Project Manager flow using parts from the ADW library database…

EDAC's Emerging Companies Committee has been organizing evening seminars a couple of times a year in which Jim Hogan chats with someone with successful startup experience about what they did and what lessons they learned. Jim Hogan is today the principal...

IEDM is a meeting held annually since 1955. Historically, it has alternated between Washington DC and San Francisco every other year. However, this year was the last year that the meeting was held in DC and for the foreseeable future (they have dates...

I have been a skeptic about whether EUV was going to work. Just in case you have no idea what I'm talking about, EUV stands for extreme ultra-violet. For what seems like forever, we have been using 193nm wavelength light for lithography, eventually adding...

On October 27, the Cadence Academic Network organized the 1st Cadence Academic Workshop in Israel. More than 20 professors as well as PhDs and master students from five major Israeli universities attended the workshop at Bar Ilan University. The first...

In this week's Whiteboard Wednesdays video, William Chen deep dives into the implementation of multi-link, multi-protocol PHY.

https://youtu.be/1nQ0XUw7oe4

A couple of years ago, it was clear that the Cadence implementation flow required a from-the-ground-up re-creation. Nobody likes to say their old tools were not as good as they could be, but that is obviously the case when the new ones are better. And...

On Nov. 18 Dr. Patrick Haspel presented at Khalifa Semiconductor Research Center (KSRC) in the United Arab Emirates. The “Open House” event, which was organized by Dr. Mohammed Al-Mulla and Prof. Mohammed Ismail, who is Center Director, was intended to...

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling, meeting power integrity targets, managing voltage drop, and other related challenges. While the solutions aren’t simple, there are emerging techniques that offer some...

I wrote yesterday of how there is a transition going on as system companies discover that they need to do their own semiconductor design if they are to have products that are differentiated from their competition. To control their destiny, they need to...

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer to infusing the chip design process with greater efficiency.

“Twenty years ago, technology people had fun making fun of ITRS predictions,” said Nikolic during a keynote...

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies and methodologies at universities and to foster contacts to the local aligned companies. We know that students either work already at these companies, or will be...

Last year Dan Nenni and I wrote a book on the semiconductor industry through the ages called Fabless. Actually I did most of the writing and I think Dan thought he had it easy. He just had to get contributed sections from all the companies in the industry...

Cadence India organized the 10th edition of the Cadence University Program’s flagship initiative - Cadence Design Contest, in 2015. Launched in 2006, the Cadence Design Contest provides engineering students with an opportunity to showcase their talent...

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University Program and the first such initiative of this kind. In this contest, students are provided with a project problem statement along with a detailed outline and parameters...

To support academia using the latest industry-standard tools, Innovus™ Implementation System has been made available to universities. If you want to use Innovus Implementation System, please contact the Cadence university partner in your region or write...

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses on the digital front-end design tools, which means synthesis, test, and power. Almost any semiconductor seminar has power as one of the main themes. Five or ten years...

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker.

The Allegro Rules Developer and Checker allows you to develop custom fabrication and assembly rules to extend capabilities provided by Allegro PCB Designer and the Manufacturing Option. This tool provides a relational geometric verification language designed specifically for creating rules that are proprietary and custom to an original equipment…