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1. Voltus-Fi Power Analysis Support and Power Grid View Generation—Voltus-Fi to Voltus Flow

The Voltus-Fi to Voltus flow provides the complete Cadence power integrity solution for full-chip power integrity analysis for all designs, featuring accurate transistor EMIR analysis and high-quality analog IP grid modeling. This application note covers the process of Voltus-Fi flow based on the 28nm…

What is WiGig

WiGig is the name given to a high-speed multi-gigabit wireless communications standard over unlicensed 60GHz radio frequency band established by the Wireless Gigabit Alliance in 2007. Since then it has become part of the WiFi Alliances and established as one of the IEEE 802.11ad protocol. As part of the WiFi Alliances, WiGig tri-band-enabled devices will operate in the 2.4, 5 and 60GHz radio band.

WiGig…

In this week’s Whiteboard Wednesdays, Chris Rowen takes a look at the basic energy equation for processors and how a configurable processor architecture provides the flexibility to optimize power for a given application. 

http://youtu.be/gMrUIqovAIU

'Tis the end of an era, folks. It should not be a surprise, but IC 5.1.41 reached End of Support as of 12/31/2014.

1.  Where do I find the support lifecycle dates (e.g., End of Support) for Cadence releases?

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od000000051SLEAY&pageName=ArticleContent

2.  Where do I find the product lifecycle letters?

https://support.cadence.com/apex/ArticleAttachmentPortal…

The 16.6 Allegro PCB Editor release ‘Find by Name’ list now supports hierarchical database objects - Diff Pair, Match Group, Region, for example:

16.5 Find by Name:

16.6 Find by Name:

Read on for more details …

Invoke the ‘Assign Color’ command.

Select ‘Diff Pair’ from the ‘Find by Name’ list.

Click the ‘More’ button.

Select a few Diff Pairs from…

After reading the rest of this blog, you might guess the truth, which is that my "designing" skills go back to the 8086 processor! In this blog, I have used a 64-bit register (Well, I could make it 16-bit, but…)  in the example, just to show that this issue is still relevant today.

At any rate, the e verification issue that I describe here seems to be a common issue for many users.

Assume that, in the…

In this week's Whiteboard Wednesdays video, Herbert Rivera-Sanchez discusses the Cadence Verification IP (VIP) Ease of Use Project. This project addresses three main areas of concern: works out of the box, provides consistent integration and provides basic training to quickly bring customers to a productive level in a short time.

http://youtu.be/fbsyfdPq4ho

A customer working on a VIP component identified that the performance of one of their protocol checkers, written in ‘e’, is significantly worse than the performance of the competing solutions. Profiler reports of a representative test case pointed to a few complex methods, which consumed about 90% of the time. What stood out in these methods was the use of the pop0() pseudo-method on a couple of list buffers. This…

Hello my fellow Digital Designers,

I'm sorry I haven't been around the blogs much lately. We've had a lot of exciting design work going on that has kept me pretty busy. I hope all of you are having a great 2015 so far. Just a heads up - all links below require a Cadence Online Support account.

Our Educational Services team has been busy putting together some short videos called Training Bytes. These are…

This year’s Mobile World Congress (MWC) in Barcelona, March 2-5, should be the largest, most exciting MWC ever. I’ve been going since 2006, and I’ve seen the show outgrow the old convention area and now, with over 1900 exhibitors, outgrow the new Fira Gran Via. We’re lucky that the Tensilica group has been going for a long time, as getting a space to exhibit now is almost impossible.

Our booth…

In this week's Whiteboard Wednesdays, Avi Behar follows up on his earlier video on the ARM® AMBA® protocol family. Watch this video for a deep dive on each of the protocols in the ARM AMBA family to learn how they are commonly used.

http://youtu.be/LQ5UVwEwZv4

CDNLive Silicon Valley 2015 will be held Tuesday and Wednesday, March 10-11, at the Santa Clara Convention Center. For the first time, we’ll have a very interesting 2-day IP track at the conference. Sign up now!

Check out our exciting agenda in Track 7. Some of the highlights include:

• External Memory Architectural Choices for Terabit-Class Devices by Broadcom
• Applying Maslow’s Hierarchy of Needs to IP Reuse…

Cache coherency is not unique to the new ARM® AMBA® 5 CHI (Coherent Hub Interface) specification that enables processors to work together in high-performance, coherent processing “hubs”, and to deliver the high data rates that are common in enterprise markets, such as servers and networking. Coherent architectures have existed for many generations of CPU designs, but verifying adherence to coherency rules has always been…

In this week's Whiteboard Wednesdays video, the last in a three-part series, Kevin Yee explains how MIPI UniPro is becoming a popular standard for chip-to-chip communications.

http://youtu.be/maQXxumlKys

The sparkle seems to have gone out of the Internet of Things (IoT) market for the moment, and this is a problem because it means my Star Trek lifestyle is now on hold.

The ambitious Google Glass project was shelved recently amid tepid market response and cultural backlash. The smart watch market has yet to ramp to early expectations; people seem to be waiting for Apple’s version.

Wearables and other IoT devices…

Functional Verification Debug Blog - SimVision Gems

 Most engineers are familiar with the “Butterfly effect” – the notion that a small change can result in enormous repercussions in the future. A similar notion applies in verification. We might expect waveform traces to match between, say, an RTL simulation and post-synthesis gate-level design for a certain signal, but we want to be sure. We want to ensure no small…

This week, you can view a couple of videos where customers describe how they used Cadence's Allegro TimingVision technology to achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems of their designs and the IPC-2581 design data format and Allegro PCB Editor tools to eliminate surprises at the final stages of PCB design.

Routing boards with high-speed interfaces had been a time-consuming, manual…

Happy New Year to all from the award-winning Virtuosity blog team (Alice, Praveena, Rajesh and myself)!  Okay, so it was an internal Cadence Standing Ovation Team Award, but it works for me.

There are few things I love more than learning and every month (or two) when I look through the new content, I am delighted to see how much high-quality material is available to highlight new features and help you use our software more…

This week, you can view a video where a customer describes how they used the Cadence® Sigrity™ PowerSI® tool to enable their team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more.

Nexus Technology
At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their…

In this week's Whiteboard Wednesdays video, the first of a two-part series, Avi Behar explains the ARM® AMBA® (Advanced Microcontroller Bus Architecture) protocol family. Many of the protocols, from Advanced System Bus (ASB) and Advanced Peripheral Bus (APB), to Advanced Traced Bus (ATB) and Coherent Hub Interface (CHI), are discussed.

http://youtu.be/fkumTBDElsU

The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving application.

Thieving outline: New ‘Rectangle’ option added to the list. If selected, the user is required to make only two digitizations of a rubber-banded rectangle.

Thieving style: A new ‘Line’ setting has been added to the existing ones of ‘Circle’ and ‘Rectangle’. The fill elements will be created as actual cline/line segment…

High-performance and high-speed memory design characterized by low-power operation are requirements for today’s leading edge electronics. Cadence is a leader in providing advanced process node, low-power memory IP. Recent news with Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and HiSilicon Technologies Co. Ltd highlights our collaboration to meet the needs of industry leaders in this area. This is the first customer…

LAS VEGAS—In the cacophony of CES, it’s refreshing to find an escape. I found mine in a set of headphones slipped over my ears.

Standing in the Cadence booth chatting with Yipeng Liu, with Cadence audio product marketing,  I’m listening to audio using DTS  Headphone:X technology.

As Liu said, “hearing is believing.” If you close your eyes, you find yourself in a room with the audio. It’s a strange experience…