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System, PCB, & Package Design : OrbitIO/SIP-XL Co-Design Flow Highlighted at CDNLive SV 2014

TeamAllegro

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. (See the complete two-day agenda.) Track 6, IC Packaging/SI, PI, featured customer papers on co-design as well as sign...
- 8 Apr 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Comparing 3D Memory Solutions and Their Market Applications

References4U

In this week's Whiteboard Wednesdays, Scott Jacobson completes his three-part series on the Memory Wall with a discussion on the different 3D memory solutions today and their market applications. You may recall that in the first segment, Scott examined how CPU performance outstrips memory transfers, and discussed options available to system designers, such as 2D solutions. In the second part of this series, Scott, took…
- 8 Apr 2014
Analog/Custom Design: Mismatch Contribution Analysis in Virtuoso Analog Design Environment GXL

Lorenz

When Monte Carlo analysis shows device mismatch variation has become problematic, Virtuoso Analog Design Environment (ADE) GXL Mismatch Contribution Analysis can provide useful diagnostics as a next step. Mismatch Contribution helps in identifying the most important contributors to the variance of the outputs. You can also compare the relative importance of the contributing instances. The analysis results can aid in making…
- 2 Apr 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Understand USB Controllers and Their Performance Specs

References4U

In this week's Whiteboard Wednesdays, Jacek Duda provides an informative overview of USB controllers and the potential performance that can be achieved. He also discusses in detail specs for USB 2.0 and USB 3.X.

www.youtube.com/watch
- 1 Apr 2014
System, PCB, & Package Design : Cadence Sigrity Full-Wave 3D Field Solver Technology Highlighted at CDNLive SV 2014

TeamAllegro

The Cadence user group event in Silicon Valley, CDNLive SV 2014, had a number of different focused topic tracks at the event. For the complete two day agenda, click here. Track 6, the IC Packaging/SI, PI featured customer papers on co-design as...
- 28 Mar 2014
System, PCB, & Package Design : Balance Metal Coverage Across Different Layers with Ease Using Cadence 16.6 IC Packaging Layout Tools

Jeff Gallagher

To maximize yield and achieve optimum quality of your final, manufactured IC package substrate, we all want to balance the metal coverage across different layer - and region - pairings of your package layout. But, just how do you go about doing that ...
- 26 Mar 2014
Whiteboard Wednesdays: Whiteboard Wednesdays—The Exploding Variety of New Interfaces for Mobile SoCs

References4U

In this week's Whiteboard Wednesdays, Tom Hackett focuses on the wide variety of new and updated mobile interfaces for mobile SoCs. These interfaces are broken down into three catagories—SoC fabric, memory, and chip-to-chip—and include ARM AMBA 4, ARM AMBA 5, OCP, DDR, LPDDR, LPDDR3, LPDDR4, Wide I/O, Wide I/O2, DRAM, eMMC, eMMC5, UFS, CSI-3, SoundWire, USB, PCIe, and SSIC.

www.youtube.com/watch
- 25 Mar 2014
System, PCB, & Package Design : What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

Jerry GenPart

While there are several videos available for Allegro Design Entry HDL (DEHDL) in Cadence Online Support as well as in the product installation documentation folder ($CDSROOT/doc), there are times when a new specific video is produced for product features. Of course, there are many videos available for all the SPB products. Recently, several new videos have been produced for some of the more common functionality areas…
- 24 Mar 2014
Analog/Custom Design: Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Tom Volden
Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects, often from one process node to another. Additionally, migration is also required for:
Second sourcing on a similar process from a different foundry
Reusing IP in next…
- 21 Mar 2014
System, PCB, & Package Design : What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!

Jerry GenPart
There are two new use models for PCB designers using Allegro Design Workbench (ADW) in 16.6. In 16.5, only a single PCB designer could work on the physical view of the design at one time.

Now, the 16.6 Team Design Authoring (TDA) - also known as the Team Design Option (TDO) in ADW - supports two use models:
Only a single designer can work on the physical view of the design at one time
Multiple physical designers can work…
- 18 Mar 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Why Cadence Verification IP (VIP) is a Smart Choice for SoCs

References4U

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500 customers consider Cadence Verification IP to be the S.M.A.R.T. choice when looking to verify their SoC designs.

www.youtube.com/watch
- 18 Mar 2014
Verification: Cadence Announces Verification IP for MIPI SoundWire and C-PHY

Moshik Rubin

Anyone who has been involved in designing mobile devices in recent years is familiar with the MIPI alliance -- a non-profit organization, which took the mission to standardize all interfaces of mobile device systems: from the camera sensor through the RF, all the way to the battery and ultra fast PHYs -- 30 different specifications!
But that’s just the beginning. The MIPI engineers don’t stand still and are working…
- 12 Mar 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - New MIPI Interfaces: Winners or Losers?

References4U

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a deeper look at the MIPI protocols that are the leading choice for certain mobile interfaces. Even though MIPI protocols are a top choice, however, they are being challenged by mobile versions of PCI Express and USB. Given this landscape, what does the future look like for MIPI and its challengers? Watch this short video to find out…
- 11 Mar 2014
Verification: The Importance of Ecosystems in the Internet of Things Era

fschirrmeister

As we develop electronics in early 2014, the battle between processor architectures is raging in all spaces, from deeply embedded through mobile to servers. Choosing the right ecosystem partners is crucially important, and today's announcement of...
- 11 Mar 2014
Analog/Custom Design: Fast Yield Analysis and Statistical Corners

Lorenz

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random, Latin Hypercube, and Low Discrepancy Sequence. More accurately, Spectre provides the engine and ADE XL interfaces with the simulator to complete the Monte Carlo analysis task. Random is the standard random sampling method. Latin Hypercube (LHS) is an enhanced method that converges faster. Low Discrepancy Sequence (LDS) is the most recently…
- 10 Mar 2014
Verification: Randomizing Error Locations in a 2D Array

teamspecman

A design team at a customer of mine started out with Specman for the first time, having dabbled with a bit of SystemVerilog. I can't reveal any details of their design, but suffice to say they had a fun and not-so-simple challenge for me, the outcome of which I can share. Unlike some customers (and EDA vendors) who think it's a good test for a solver to do sudoku or the N-Queens puzzle (see this TeamSpecman blog…
- 10 Mar 2014
SoC and IP: RealTek Shows New HiFi-based Codec with Software from Sensory and ForteMedia

PaulaJones

Watch these demonstrations of RealTek's new ALC5677 audio codec - which uses HiFi EP running software from Sensory and ForteMedia.

http://youtu.be/VMPOhU_rYuM

In the above demo, Jason from RealTek shows how ForteMedia's iS620 noise processing software can be used for multi-microphone voice processing. iS620 dramatically improves the user experience in voice communication and voice recognition for smartphones.…
- 10 Mar 2014
Analog/Custom Design: Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence Online Support

stacyw

Time just got away from me last month, so here's two months worth of new content for your browsing enjoyment...
Videos
1. Integration Constraints Capability used in Mixed Signal Design Implementation
Explains and demonstrates the integration constraints capability of the Cadence Mixed-Signal Solution.
2. Virtuoso Floorplanning Design Flow Demo
Demonstrates the Virtuoso Floorplanner Flow: soft and hard blocks, defining cell…
- 7 Mar 2014
System, PCB, & Package Design : Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout Editors

Jeff Gallagher

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility that allows them to extend and modify the tool to meet their specific requirements. This might mean custom SKILL tools developed in-house, scripts/macros to automat...
- 5 Mar 2014
Whiteboard Wednesdays: Whiteboard Wednesdays—How 2D Solutions Help Close the Memory Wall Gap

References4U

In this week's Whiteboard Wednesdays episode, Scott Jacobson deep dives into 2D memory solutions like EMMC 5.0, UFS, and DDR4. Scott highlights how these solutions can help address CPU performance and power requirements and memory ability to deliver to these needs.

www.youtube.com/watch
- 4 Mar 2014
SoC and IP: MIPI Protocols—Making Mobile Happen at MWC

PaulaJones

MIPI protocols are expected to ship in over 4 billion mobile devices this year. That's billion with a "b".

Every year, new products are introduced at Mobile World Congress in Barcelona. Without MIPI interfaces, these products would not be able to perform nearly as well. You may not have heard about CSI-2, DSI, D-PHY, or many of the other MIPI standards, but thankfully there's the MIPI Alliance, a global…
- 3 Mar 2014
SoC and IP: Android Audio Offload Explained at Mobile World Congress

PaulaJones

Want to lower power in your next Android^TM device? Look to the industry's first Android-compatible technology for a licensed audio DSP. The Tensilica® HiFi Audio Tunneling for Android takes full advantage of the enhancements in the recent KitKat release to prolong battery life, cutting audio processing power by up to 14X, which results in double the smartphone playback time.

How does this cut the power? By completely…
- 3 Mar 2014
Verification: New Incisive Verification App and Papers at DVCon by Marvell and TI

Pete Hardee

If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement back on January 13^th that Incisive Formal technology, with our new Trident cooperating multi-core engine, took top billing. But you would have needed to be very diligent to have followed the link in the press release to the Top 10 Ways to Automate…
- 27 Feb 2014
System, PCB, & Package Design : What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has Several New Enhancements!

Jerry GenPart

The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report on hierarchical nets.

Read on for more details …

Just a quick post this week to share with you a couple new capabilities in the DEHDL Cross Referencer.

There is a new option to generate Cross References using nets from all levels of the schematic hierarchy:

Each net instance contains Cross References for the net instances across…
- 26 Feb 2014
Verification: Incisive vManager at DVCon - Come See It!

John Brennan

Have you heard the news? There is a new version of vManager announced this week, right in time for DVCon. vManager has been completely re-architected to be a database driven environment, scaling to multiple users and supporting gigascale size designs.. And, with ever growing verification requirements there is now a need for highly coordinated verification teams. With 100x more scalability and 2x greater verification productivity…
- 25 Feb 2014

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