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The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database and alternate units.  Alternate unit display requires the enablement of the user preference variable ‘showmeasure_altunits’. ‘Show Measure’ also supports a measurement between padstacks even if a common layer does not exist. This will be helpful when measuring mask-related geometry to conductor.

Read on…

Why high yield analysis?

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4 technology. He also walks you through the improvements of DDR4 over DDR3, as well as the memory standard's specifications and the challenges of meeting these specifications.


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Embedded Vision Summit West 2014 on May 29 at the Santa Clara Convention Center provides a unique opportunity for engineers to learn about the hottest technology in the electronics industry: embedded computer vision, which enables "machines that see and understand."

Summit highlights include:

• Keynote talks by industry luminaries from Facebook and Google
• Two technical conference tracks featuring "how-to" presen…

In this week's Whiteboard Wednesdays, Tom Hackett takes a closer look at simulation verification IP (VIP), and how these IP cores help verify designs with protocol checks, test sequences, and other capabilities.


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For years we've watched the e and SystemVerilog race via countless presentations, articles, and blogs. Each language is applied to SoC verification yet the differences are well documented so any comparison is subject to recoding from one language to the other. This makes a direct performance comparison difficult to measure. Until now.  

On April 21, 2014, SystemVerilog and e toed the line for the first direct SoC race…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on which engineering group was responsible for final assembly, one part would be treated as a black box and the two parts would be bolted together at the system-on-chip (SoC) level. But today's mixed-signal designs have multiple…

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless transceivers and protocol standards 802.11x and LTE/LTE-A. Wireless transceiver implementation options consisting of RF, Analog Front-End (AFE), and Digital components are examined.


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In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3.  Here are more new features that are now available in Virtuoso ADE XL in the recently released ISR6.

• Notes can be added to tests, variables, corners, parameters, and histories. This allows you to document information about important items in your setup…

Hi All,

Here's another great new feature that I've found very helpful...

Broadband SPICE is a new tool for S-parameter simulation in Spectre RF.

In the MMSIM13.1.1 (MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...

Hi Folks,

A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job?  I use distributed processing and need to provide an estimate before submitting jobs."

The...

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means to "take command of MIPI PHYs". This is a first of a three-part series on the topic. Here, Kevin will introduce you to D-PHY and its architecture, and how the protocol meets the requirements of mobile devices.

www.youtube.com/watch

Anyone who has ever played a musical instrument knows how hard it can be to keep the instrument in tune when subjected to variations in weather conditions. Heck, in 2009, Yo-Yo Ma and friends (sorry, he gets top billing because I used to play the cello) pantomimed their performance at the Presidential Inauguration because their instruments wouldn't function properly in the frigid temperatures. Guess they didn't want to…

Highlights for this month include lots of useful Physical Verification System (PVS) appnotes and several blog articles on advanced analyses and flows in Analog Design Environment (ADE) GXL.

Application Notes

1. Physical Verification Checks and Generic Tips

Concise overview explaining the basics of the various DRC and LVS checks in rules files.

2. Recommendations and Tips for the PVS DRC Flow

Includes sections on…

The 16.6 release of OrCAD Capture has a couple new productivity enhancements centered around how reference designators are assigned to components in the schematic.

Read on for more details …

Design Level Auto-Reference Designator Assignments
In 16.6, in addition to the schematic level annotation of reference designators, you can also perform a design level annotation by selecting the Design Level option:

The previous…

Development Model for ADE and ViVA

Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR.  These content ISRs receive additional usability testing, product validation, and demonstrations and beta testing with customers. This development model gives R&D long enough development cycles to add meaningful content while ensuring that quality and stability…

In this week’s Whiteboard Wednesdays, Charles Qi introduces an emerging new application called Hosted Virtual Desktop, which supports increasingly mobile workers who want to use any smart, connected device to access corporate data resources.  Charles goes into detail about how Cadence IP can help expand the application to help businesses make mobile workforces more efficient.

www.youtube.com/watch

In my first blog of this quarterly series, I focused on how Rapid Adoption Kits (RAKs), developed by Cadence engineers, are enabling our users to be productive and proficient with Cadence products and technologies.  

In this second quarterly blog, let me explain the "Once Resolved, Reused Forever" internal process for documenting knowledge on https://support.cadence.com/. It ensures that we are not solving a problem…

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/

Rapid Adoption Kits:

Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2

With the help of this RAK (rapid adoption kit) you will learn how to perform static…

Over the past couple of years there has been some interest in applying a software development technique called unit testing in the hardware development flow. One of the reasons is that unit tests allow customers to validate their testbench in isolation, enabling very fast and thorough tests. Some customers have developed their own framework to accomplish this testing. In the Incisive 13.2 release, Cadence has introduced…