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In this week's Whiteboard Wednesdays, we take a little different approach and show you a fun and fast way to understand how Cadence® Tensilica® Xtensa® processors work, and how you can easily use them to offload your applications processor. After the video, learn more about Xtensa processors here: http://bit.ly/1xZfYdP. 


www.youtube.com/watch

Excuse the tennis analogy, but just coming out of Wimbledon!  However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take"  between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course…

Application Notes

1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40) LVS

Shows you how to put in place the PVS(LVS)-QRC(av_extracted) view using TSMC files.

Videos

2. Mismatch Contribution in Virtuoso Analog Design Environment GXL

Mismatch contribution analysis is a Monte Carlo post-processing feature that helps in identifying the important contributors to mismatch variation. You can then modify…

The register and memory package vr_ad for Specman is used in pretty much every verification environment. In most cases today, the register specification is captured in an IPXACT description and the register e-file can be automatically generated from it.

The vr_ad package comes with a variety of pre-defined register access policies, which cover the typical register usage.

However, many users have the need for special…

The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the PCB Design team experiences in the physical team design flow.

Flexible Boundaries
Designed to reduce the number of iterations between the master and partition designers, it’s now possible for partition designers to move components…

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below.

Read on for more details …

IPC 2581 Overview

PCBs have changed significantly over the past three decades, yet to the surprise of many, we still commonly use 30-year-old ways of communicating design intent to manufacturing. These decades…

Hi Folks,

Check out this great new video on YouTube:

CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS

In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members' review, just in time for the annual Developer Conference at Santa Clara, CA, next week (June 4-5).

The Gen4 spec was announced 2.5 years ago with the 'usual' objective - doubling the bandwidth while keeping backward compatibility. Sounds easy, doesn't it? Well - the time it took to get to rev 0.3 hints that it's not a trivial…

In this week's Whiteboard Wednesdays, Kishore Kasamsetty discusses the low-power advantage that LPDDR4 provides over the LPDDR1/2/3 in the mobile market.

www.youtube.com/watch

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while routing across fiberglass substrates. Other routing applications may be applicable as a result of this implementation, including, but not limited to, package/connector breakout or routing associated with tester cards.  

The Offset…

Plenty to keep you busy this month.  Lots of RAKs, videos, and new Quick Start Guides and FAQs.

Application Notes

1. Using Annotation Browser with Virtuoso IPVS

Learn how to invoke the Annotation Browser and have it always appear docked to a specific location of the layout window, how to customize the Annotation Browser, and how to automatically set the visibility of the error markers.

2. AMS Designer INCISIVE Command…

This year, the Design Automation Conference (June 1-5 in San Francisco) has put a lot of effort into great content for IP buyers, and Cadence has great plans to highlight our IP. Here are some of the things you can see at DAC this year:

Booth 2610 demo 

See Cadence's large library of IP and verification IP for memories, interfaces, analog, and peripherals. Join us for a fun-filled game and test your knowledge of the protocols…

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase Noise Profiles.  We now have an easier way to do this.  

Starting in MMSIM 13.1, you can specify the phase noise as an instance parameter in Spectre sources, including port...

In this week's Whiteboard Wednesdays, the second installment of a three-party series, Kevin Yee continues his earlier discussion on "taking command" of MIPI PHYs. Here, Kevin discusses M-PHY, its architecture, and the protocol's functionality in mobile devices.

www.youtube.com/watch