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Whiteboard Wednesdays: Whiteboard Wednesdays - How the MIPI Alliance Works to Enhance Mobile Devices

References4U

In this week's Whiteboard Wednesdays episode, Moshik Ruben, Product Marketing Director at Cadence, highlights the MIPI Alliance's focus on standardization to help improve today's mobile devices. Moshik discusses MIPI protocols including CSI-2, DSI, D-PHY, SLIMBUS, M-PHY, UniPro, UFS, CSI-3, LLI and DDRF. This year alone, these protocols are projected to be shipped in over 4 billion mobile devices.

www.youtube…
- 25 Feb 2014
Analog/Custom Design: What's the Worst that Could Happen?: Worst-Case Corners in ADE GXL

stacyw

In addition to combinations of temperature range and power supply voltages (usually more than one), the process design kit which landed on your desk yesterday presented a bewildering alphabet soup of device corner combinations which you need to consider when verifying your circuit design.
Fast/slow, high/low, pre/post. If I have to spend the time to run all the possible combinations, I won't have much time left to tune…
- 24 Feb 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Implementing Always-On Audio

References4U

In this week’s Whiteboard Wednesdays episode, Gerard Andrews, from the Tensilica Audio DSP Group at Cadence, discusses always-on audio functionality. Gerard details features like voice trigger, sensor fusion, and low-power audio playback, and explains how Cadence’s HiFi DSP solution can help you successfully implement always-on audio technology in today’s mobile devices.

www.youtube.com/watch
- 18 Feb 2014
Analog/Custom Design: What Your Circuit Doesn't Know, Can Kill It!

NewYorkSteve

Device variation has been a long-standing problem in custom design. Over the years, our customers have made many attempts to model the behavior though parameterization, simulation model extensions, sub-circuits, and by just "guessing" as to what might happen. As the mathematical complexity of each node increases, so does the difficulty of making sure all the design possibilities…
- 14 Feb 2014
System, PCB, & Package Design : Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD and SiP Layout Tool

Jeff Gallagher

In this week's discussion, let's take a look at a cornerstone of every good substrate design: plane shapes and voiding. In particular, what do you do if you need to void around an object on one or more layers of the object itself, whether a c...
- 13 Feb 2014
Verification: e Language Editing with Emacs

teamspecman

Specman and e have been around for a while, and some clever people have developed a nice syntax highlighting package for Emacs. What does this package do? Well, have a look yourself:

Editing in Emacs with the Specman mode
And

Editing in Emacs without the Specman mode
As you can see, the Specman mode gives you syntax highlighting, automatic indentation, it detects comments and shows them in different font or color if…
- 12 Feb 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - What is VIP?

References4U

Today, our continuing Whiteboard Wednesdays video blog series will provide an overview of Verification IP and how it helps test today’s complex SoCs.

Watch this week's episode to hear Tom Hackett, product marketing director at Cadence, talk about the important role that VIP plays in the verification process. Tom details how VIP provides known good designs and stress testing for all interfaces and memory components…
- 11 Feb 2014
System, PCB, & Package Design : What's Good About Allegro/OrCAD/Sigrity Quarterly Incremental Releases (QiRs)? Check Out 16.6!

Jerry GenPart

You’ve no doubt seen announcements (either via customer emails, on the Cadence website, on the Cadence Customer Support portal, etc.) about Quarterly Incremental Releases (QiRs). QiRs have been made available for over a year now with a focus on updates to the 16.6 release.

In case you’re not familiar with QiRs, they are an exciting new way of bringing Cadence users valuable new features without having to wait for…
- 11 Feb 2014
Verification: Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online Support Recently

SumeetAggarwal

There is always a demand, in most corners of the world today, for learning and troubleshooting something simply and quickly. Most users of any product or tool want access to a self-service knowledge base so that they can go and troubleshoot the issue on their own. They do not really want to sit through a long training class and also pay money; rather, they are of the type who have the knack to figure things out on…
- 11 Feb 2014
SoC and IP: My Love-Hate Relationship with Mobile World Congress

PaulaJones
My friends are jealous. I get an all-expense-paid trip to Barcelona, Spain to see the latest and greatest mobile technology at Mobile World Congress (MWC). They don't believe it when I tell them I love the yearly trips to Barcelona, but also hate it.
What I love about Barcelona and MWC:
Staying in the Gothic quarter, with all the good food and entertainment.
The nice busses we rent that take us directly to and from the…
- 5 Feb 2014
Whiteboard Wednesdays: Whiteboard Wednesdays—Imaging, Video, and Embedded Vision

References4U

Today, our continuing Whiteboard Wednesdays video blog series will shed some light and provide practical insights on imaging video.

In this week's Whiteboard Wednesdays episode, Gary Brown, from the Tensilica Imaging and Video Division at Cadence, talks about imaging, video, and embedded vision technologies that are being worked on today. Gary gives a high-level overview of the industry sectors and end products that…
- 4 Feb 2014
Verification: Cadence and AMD Add New UVM Multi-Language Features

Adam Sherer

The UVM Multi-Language Open Architecture open-source library was recently updated with new features. The hallmarks of this solution continue to be the ability to integrate verification components of multiple languages and methodologies at the testbench level, expanding beyond simple connectivity at the more limited data level, and the multi-vendor support.

Interestingly, multi-language is a bit of a misnomer…
- 4 Feb 2014
SoC and IP: Latest Developments in Ethernet Standards

ArthurM

Cadence is committed to supplying Ethernet silicon and verification IP to help its customers develop Ethernet solutions. The IEEE 802.3 Ethernet standards committee recently held an interim meeting in Indian Wells, California.

The location and weather were good.

And I got to see a joshua tree:

I blogged about the progress being made with Ethernet standards last December. Here is an update from the January meeting:

802.3bj…
- 3 Feb 2014
System, PCB, & Package Design : What's Good About Allegro PCB Editor CM Analysis Control? 16.6 Has a Few New Enhancements!

Jerry GenPart

Beginning with the 16.6 version of Allegro PCB Editor, you can now toggle the Analysis flag directly from the Constraint Manager (CM) column header without using the “Analysis Modes” dialog.

Read on for more details …

The Constraint Manager column’s header is colored in yellow in case the related Analysis is set to OFF.
Here is a screenshot from the Electrical Worksheet > Net > Routing > Wiring…
- 3 Feb 2014
Verification: Covering Edges (part II)—“Inverse Normal” Distribution

teamspecman

In the previous example, we used the "select edge" to generate edge values for fields. But in many cases, what you really want to generate is not the exact edge, but "near the edges". For example, for a field of type uint (bits : 24), generate many items whose values are 0..4, and many of 0xfffff0..0xffffff. To achieve this, you can call this "the inverse normal distribution" and give more weight to the edges.…
- 29 Jan 2014
Whiteboard Wednesdays: Whiteboard Wednesdays - Closing the Memory Wall Gap

References4U

We're excited to introduce Whiteboard Wednesdays, a new video blog series that will shed some light and provide some practical insights on how to address a variety of intellectual property (IP-) related design challenges. Our inaugural segment addresses the memory wall gap--that phenomenon that occurs when the bandwidth of microprocessors outpaces the bandwidth of the memory in the design, degrading system performance…
- 21 Jan 2014
System, PCB, & Package Design : What's Good About Allegro PCB Editor New Ratsnest Display Option? Check Out 16.6!

Jerry GenPart

The 16.6 Allegro PCB Editor release has a ratsnest display option that is designed to reduce the density of rat display in the workspace. Rats seen as pass-through, ones not terminating to a pin in view, are automatically filtered from the display.

Read on for more details …

1. Enable the new rat display option by selecting Display > Show Rats > End in View Only.
2. This feature will make much more of an impact…
- 21 Jan 2014
Verification: ADI Success Verifying SoC Reset Using X-Propagation Technology - Video

Adam Sherer

Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology they applied to reset verification and eight bugs they found during the project. We were able to catch up with Sri Ranganayakulu just after his presentation and captured this video explaining the key points in his paper.
Sri had…
- 19 Jan 2014
Analog/Custom Design: Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Support

stacyw

With this month's title, I'll need to start adding the year, as this marks the one-year anniversary of the montly series. I know it's been a useful monthly exercise for me. Hopefully it has been helpful for everyone out there as well.
Application Notes
1. How to Utilize a Windowing Technique for Accurate DFT
Explains the best way to set up a transient simulation in ADE in order to achieve good results when performing…
- 17 Jan 2014
System, PCB, & Package Design : See the Differences Between Your Designs Visually with the Layer Compare Toolset in 16.6 APD and SiP Layout Tools

Jeff Gallagher

Have you ever wondered exactly what has changed between two different versions of a package substrate? Perhaps you've wanted to see exactly what metal on the top surface of your package is exposed through the combination of solder mask openings a...
- 15 Jan 2014
Verification: Recap of Another Successful Japan C-to-Silicon User Seminar

Jack Erickson

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They host about two per year, and the meetings have been growing in size and content. The November session drew 44 customers, representing 13 companies. The content spann...
- 13 Jan 2014
Digital Design: Five-Minute Tutorial: Start the New Year with Voltus

Kari

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone new who is stopping by to check us out. We're glad you're here and we hope you'll hang out with us for a while!

I thought we could start this new year with one of Cadence's newest tools: Voltus IC Power Integrity Solution. You can read all the official details in this news article, but if you're a digital designer like…
- 9 Jan 2014
System, PCB, & Package Design : What's Good About AMS Multi-Core Engine Support? It’s in the 16.6 Release!

Jerry GenPart

The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities. There are several runtime options available to enhance the performance of simulation runs.

Read on for more details…

Performance of multi-core capabilties is enabled. There are focused performance enhancements for large designs with complex model instances like MOSFETS and BJT. In addition, I/O performance improvements with…
- 8 Jan 2014
System, PCB, & Package Design : Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor

Naveen

Over the time, jumpers have found their importance in multiple applications. The following blog is aimed to provide more insight on their usage and implementation using Cadence Allegro PCB Editor.
What is a jumper? A wire jumper is typically a short wire used to electrically connect two points. On occasion, a wire jumper is necessary on a single-sided PCB to continue the signal connection over a group of etch traces. The…
- 7 Jan 2014
Verification: New Capabilities in the C-to-Silicon Compiler 2013 Releases

Jack Erickson

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular. We saw our customers take on over 75 new projects using C-to-Silicon, much of that coming from expanded adoption within our existing customers. These designs spa...
- 6 Jan 2014

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