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The future of television is being defined by two key technologies: organic light-emitting diode (OLED) screens and ultra high definition (Ultra HD or "4K TV") standards. OLED is a display technology that makes colors pop like nothing you've seen before. 4K TVs deliver incredible sharpness and detail by packing in four times as many pixels as there are on the 1080p HDTVs in our living rooms.

Today HDMI 1…

In the following paragraphs several inferior functions will be presented: portable_1, copyTable_2, copyTable_3, copyTable_4, and copyTable_5. Finally three useful robust functions will be presented (copyTable, getHa…

Ever wondered how to switch on all messages, or how to switch all of them off? Or get confused by the output from the "show message" command?

You're not alone. Many users and even Cadence R&D engineers have struggled with this. The main reason for the confusion is that messages are controlled by loggers, and…

In most FPGA-based boards, the PCB designer is on his own -- with little help from any tool -- to unravel what is often a routing nightmare. This can be caused by FPGA and/or schematic designs that have given little thought to the actual routing, inclucing layer stackup, crossovers, differential pair length matching, and high-speed signal integrity requirements. 

To be fair, this is not completely the fault of the upstream…

The Allegro FPGA System Planner (FSP) has the ability in the 16.6 release to import Allegro PCB Editor .brd file contents.

Read on for all the great details …

To import an Allegro design, you must first begin with a blank FSP design, otherwise this menu pick will not even appear in the Tools pull-down. Also, this menu pick does NOT import connectivity. It only imports component placement information and the board…

Feeling a bit lazy this month, but even without digging too deeply, I could find 16 new and interesting bits of content...

Application Notes

1. Adding and Managing CDF Parameters for Fluid Guard Rings (ICADV12.1)

Shows you how to add and update the Component Description Format (CDF) parameters and attributes that affect the geometry of a fluid guard ring (FGR) instance. 

2. Customizing Create Guard Ring Form (ICADV12.1 ISR3…

The 16.6 Allegro PCB Editor release provides enhanced Object Filtering to control object display in the Constraint Manager (CM) Worksheet. This feature enables you to select and filter out objects that you want displayed in the CM worksheet.

Read on for more details…

The objects for diff pair model sub-filters are in the same Filter dialog as a tree. The main level of the tree contains existing object types. Sub…

Just a very brief post this week on a new AMS Simulator (PSpice) capability.

The AMS Simulator 16.6 release allows you to undo schematic changes after you’ve done a netlist and simulation.

Read on for more details ...

1. Open a design, for example the sample design located in <$CDSROOT>\tools\pspice\capture_samples\anasim\example\example.dsn
2. Open the page and modify the value of RC1 to 12K:


3. Simulate the design…

There have been a few new library level enhancements made to 16.6 Allegro RF PCB Editor—

• New libraries
• Setup enhancements
• DRC removal for netlist re-import
• Discrete library translator enhancements

Read on for more details …

New libraries

We’ve provided two new RF components that existed in ADS:

• VIA2
• SLINO

VIA2 is a special via component in ADS, which is something like Allegro via padstack (but it’s not a padstack…

There are several new enhancements associated with the 16.6 PCB SI Channel Analysis (CA).

Read on for more details …

SigXplorer has been enhanced to provide greater flexibility associated with AMI model management. Experimentation with buffer and AMI combinations, until this release, required joining them at the library level. No manipulation could be done in SigXplorer. Now, the 16.6 release provides canvas-level…

In both previous coverage blog posts (Part I and the Part II), we showed two solutions for refining instance-based coverage in a reusable way. And in doing so, we demonstrated a case where using the instance_ignore option is more suitable than using the extension under when solution.

Now, let us modify the requirement a little, by adding a new item to the covergroup:

extend packet_generator{

  cover packet_generated…

The Shape - Add Rectangle command has been enhanced in the 16.6 Allegro PCB Editor release to support cornering options of ‘Chamfer’ and ‘Round’. Control the corner length/radius using either ‘Explicit Length’ values or as a ‘Percentage of the Short Edge’. When adding a rectangular shape, you have the option to interactively draw the rectangle or add parameterized shapes using the new Place Rectangle option. …

In the last coverage blog, we showed how the extensions of covergroups under when subtypes can help us write a reusable per-instance coverage.

We described a test case where a packet generator unit can create packets of different sizes. The packet generator unit has a field that describes the maximum size of any packet that can be generated by the packet_generator instance:

type packet_size_t: [SMALL, MEDIUM,LARGE,HUGE];

Verification regression consumes expensive compute resources and precious project time, so any speed-up has both a technical and business impact. As announced July 17, Fujitsu was able to improve both the compute resource and project time by using Cadence Incisive products and working closely with Cadence field resources to deploy them.  Results:  1.5x faster per test, 3x faster regression overall, and 30x storage reduction…

• CPM Explorer
  • Viewing project .cpm data
• Progress Controls
  • Locking/unlocking flow steps
  • Manual advance
  • Access controls – who can access flow steps
• Customizations
  • Changing the welcome page
  • Adding a corporate look and feel

After talking about some tips for using trace files in debugging Verification IP simulations in my last blog post, here I am back again, as promised. This time I'll discuss and provide references for the Denali Migration Guide, NVMe PureView VIP Usage, Verification Flow for USB, Instantiating VIP Models with SystemVerilog, and finally Integrating USB 3.0 PHY DUT with PureView USB 3.0 VIP.

1. Many users have reported…

Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed-Signal/Low-Power Focused Technology-On-Tours to Penang and Singapore later in July 2013. Cadence will showcase mixed-signal and low-power solutions aimed at designs that cater to the always connected world. With smart devices taking over our everyday lives, design teams are moving towards complex mixed-signal designs with advanced low power…

Wow!  There was an amazing amount of new content added last month.  A lot of new videos and some Really Useful articles.  Enjoy.

Rapid Adoption Kits

1. CPF-AMS Low-Power Mixed-Signal Simulation

CPF-AMS is an extension of mixed-signal simulation to help the designer simulate mixed-signal low-power design with the CPF language. It includes all CPF-related technology applicable in the mixed-signal world, such as power shut off…

Allegro Design Entry CIS provides a new feature called NetGroup, which offers an easy-to-use and more flexible method of connecting schematic symbols in complex designs using the concept of bundling and connecting signals/nets.

What are NetGroups

A NetGroup is a heterogeneous collection of nets. A NetGroup can have scalars (wires), vectors (buses), or a combination of both scalar and vector nets. It can also have other…

Cadence Verification IP (VIP) provides solutions for verifying compliance and compatibility of protocols. All VIPs include highly configurable and flexible simulation models of all protocol layers, devices and transaction types. Cadence VIPs also support integration and traffic generation in all popular verification environments.

During the past year, I have seen engineers struggling with debug for VIP based simulations…