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CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides an excellent opportunity to share your experiences and insights on key technical and industry issues. 

And it’s not just about Cadence tools.  We’re hosting a track on IP and, if we get enough papers, we'll expand this to two IP tracks.

Submit an abstract for consideration at the 2015 conference. Here’s the link with…

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence's high-performance, low-latency controller solution for PCI Express (PCIe).

http://youtu.be/lEurRUjGS2c

This week, you can view a couple of videos where customers describe how they used the Sigrity and Cadence SiP Digital Layout products to simulate, verify, and reduce the size and costs of their designs.

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk
In this Expert Insights video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified their…

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable options for Cadence 10/40G Ethernet MAC, integrated PCS, and SerDes IP.

http://youtu.be/CaQ6tPPQqA4

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film generation.

Read on for more details …

Film Domain

Artwork films can now be designated by the domain where they appear. There are four domains available; Artwork, PDF, IPC2581, and Visibility. Access the User Interface by clicking on ‘Domain Selection’. One of the benefits of the domain form is the ability to segregate films for…

Just when you thought you were done setting up EM model files, along came another advanced node with more complicated rules. Sound familiar? I've already posted two Five-Minute Tutorials about EM Model File creation—you can review them here and here—but I need to post one more.

In the more recent of the two previous posts, we ended up having to do some hand-editing. Raise your hand if you like to hand…

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training modes within the DDR interface. Watch to learn more about how these training modes can optimize timing.

The 16.6 Allegro PCB Editor release's new ‘Slide’ command utilizes a move-intersect algorithm that delivers smoother, more predictable, and localized edits. This change has allowed for simplifying the use model, integrating sliding of off-angle and arc routing, and providing new options to improve efficiency. In 16.6, the standard ‘Slide’ command has been replaced with a new version and is accessible in the same way as…

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps to select the right NAND Flash solution and ensure it meets the requirements of your design.

http://youtu.be/4n1A7ePFGNw

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing in the Ethernet space—Ethernet in cars. With its high data rate, lightweight cabling, and distributed networking capabilities, as well as the fact that it is an interoperable open standard and works well with TCP/IP, Ethernet is ideal for addressing many of the challenges facing automotive engineers.

www.youtube.com/watch

I joined Cadence in July 2000 and was immediately put on a three-month training to learn and understand the simulator tools. There were formal training sessions, and I had a mentor who I could ask all my queries. But most of the times, I was on my own, as "learning by doing" was the motto of my mentor. After completing 14 years at Cadence, I can tell you that it works great, especially in cases where the tool is also…

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved outside their present Class-Subclass structure. In previous releases, workarounds using the clipboard were necessary to accomplish this task.

Hover over the line, text, or rectangular element, then use the RMB to access the "Change Class/Subclass" command. Select a new class, then one of the subclasses within the Class structure from…

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind choosing the right ADC in and Analog Front End for wireless (802.11ac and/or 3G/3G) communication systems.


www.youtube.com/watch

One question we often hear from experienced physical design engineers migrating to Encounter Digital Implementation System is, "How do I get up to speed on the tool as quickly as possible?" They understand place-and-route (P&R) concepts so they often don't need to attend a full training class over several days.

Frequently, they may utilize Rapid Adoption Kits (RAKs), documentation, and other material…

I wrote earlier that the sheer vastness and potential for IoT designs require a different way of thinking about system implementation. There just isn't a single controller architecture that meets all IoT requirements, such as multiple sensors, an innovative user experience, wireless protocol support, and various security requirements.

And if a single controller architecture is not the answer, do we just lean on other…

The Tensilica® group at Cadence has just published a 37-page application note on a Wi-Fi 802.11ac transceiver used for WLAN (wireless local area network), and it's full of really useful information.

This transceiver design is architected on a programmable platform consisting of Tensilica DSPs, using an anchor DSP from the ConnX BBE family of cores in combination with a smaller specialized DSP and dedicated hardware…

The Allegro Design Entry CIS (OrCAD Capture) 16.6 release provides extensions to the Design Rule Checks (DRC) system. The Custom DRC provides the ability to extend the Capture DRC system to user-defined rules.

Open an Allegro Design Entry CIS design database (.dsn) file, select a design in Project Manager, and click menu Tools > Design Rules Check:


Click on Configure Custom DRC:


The following DRCs are provided as examples…

A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:

• During manufacturing they are used to verify that a newly assembled device is working correctly. Any equipment that fails this testing is either discarded or sent for rework.
• After sale of the device to a customer, test points may be used at a…

In this week's Whiteboard Wednesdays video, Mukul Dawar provides an overview of the Mobile PCIe (M-PCIe™) specification. He explains how Cadence VIP for M-PCIe can help you verify your mobile SoC design.

Suppose you have two verification components, each driving its own portion of the DUT (for example, two protocols driving a DUT, one implemented in e and the other in System Verilog).

In this case, you would have two separate sequence-driven, end-of-test mechanisms - one for each framework.

An issue arises when one of the frameworks drops its last TEST_DONE objection. In this case, that framework will begin simulation…