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System, PCB, & Package Design : What's Good About Allegro PCB Editor ECSets and Ref Des Values? 16.6 Has a Few New Enhancements!

Jerry GenPart

Beginning with the 16.6 Allegro PCB Editor, the environment variable UPDATE_ECSET_REFDES is now the default behavior.

Read on for more details …

Most Electrical Constraint Sets (ECSets) will map based on Reference Designator (RefDes) values. It is sometimes the only thing that is unique for pins in a topology:

In this picture, U21 and U44 have the same SI model and the same pin use. So the only way to differentiate…
- 23 Oct 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Embedded Net Name Display? Check Out 16.6!

Jerry GenPart

A new graphical display option in the 16.6 Allegro PCB Editor embeds net names within the cline path, pins, shapes, and flow lines. Useful in just about any PCB application, the display of net names will be extremely valuable for those involved in design reviews or board debug. This feature is enabled by default in all PCB products and does require Open GL to be enabled. The visibility controls for traces, pins, and shapes…
- 15 Oct 2013
System, PCB, & Package Design : Why Does Signal Integrity Analysis Need to be Power Aware?

TeamAllegro

Ever since the I/O Buffer Information Specification (IBIS) committee broke away from the "signal only" mentality and approved the new standard for including power information within the IBIS spec, there has been a lot of buzz in the industry about performing power-aware signal integrity analysis. Effectively this would mean combining both signal and power integrity analysis into one.

But why does it matter?…
- 11 Oct 2013
Verification: Starting Virtual Platform Simulation with Cadence Software Developer

jasona

Last time, I provided an introduction to the Eclipse setup for the Cadence Virtual System Platform. This time I will explain how to run simulation using Software Developer. Cadence Software Developer provides multiple flows to hand off...
- 11 Oct 2013
Analog/Custom Design: Virtuosity: 16 Things I Learned in September by Browsing Cadence Online Support

stacyw

Rapid Adoption Kits
By now, I think you know what RAKs are, and that they include a detailed instructional document and database. Use the title link above to access the main landing page and browse all the available material.
1. DRD-based Interactive Compactor
The DRD-based interactive compactor can help you change the spacing between existing objects in your layout either through compaction or spreading. It can also fix…
- 11 Oct 2013
Analog/Custom Design: SKILL for the Skilled: How to Shuffle a List

Team SKILL

The previous post of SKILL for the Skilled presented some ways to systematically visit all permutations of a list. As noted, the time to iterate through all permutations of a large list is prohibitive. If the goal is to find a permutation that meets some criteria then it may work perfectly well to simply test the criteria on randomly chosen permutations of the list and continue doing so until some time-out is reached…
- 9 Oct 2013
Verification: Combining the Linux Device Tree and Kernel Image for ARM

jasona

Back in 2010, I wrote two articles about a SystemC model used to load the Linux kernel and its various artifacts into memory for ARM virtual platforms. The first was A SystemC TLM 2.0 ARM Linux Boot Loader and the second was More on the SystemC ARM L...
- 8 Oct 2013
Verification: Getting Started with the Cadence Virtual System Platform: Software Developer

jasona

Cadence Software Developer is an exciting Eclipse-based product for developing, debugging, and analyzing embedded software. It has a long list of powerful capabilities that will make your job a lot easier - including transparent and intuitive one-cli...
- 8 Oct 2013
Verification: Trends in Using Software for System Verification

jasona

There is a clear trend to use more software running on the CPUs of a design for system verification. Historically, there has always been the pre-silicon operating system boot that was performed on emulators like Palladium. Typically, the boot was abo...
- 8 Oct 2013
Verification: e Macro Debugging

teamspecman

When creating a testbench using the MDV methodology, you want to write intelligent code whose behavior can be easily modified.
Using e macros can greatly improve your productivity by raising the level of abstraction at which these testbenches are created and used. With e macros, you can reduce the amount of code and simplify usage of code that needs to be used in several places in the testbench.
e macros are powerful code…
- 7 Oct 2013
Analog/Custom Design: Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design Community

Sathish Bala

If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring one's knowledge to another person instantly).

Mixed-Signal Technology Summit, Oct. 10 at Cadence's San Jose campus, is the closest thing to a mind meld to share mixed-signal design practices and challenges…
- 6 Oct 2013
System, PCB, & Package Design : What's Good About AMS Simulator IBIS Model Capability? It’s in the 16.6 Release!

Jerry GenPart
The 16.6 AMS Simulator now provides IBIS model simulation capability:

SPICE circuit generation for all IBIS versions
Support for V-T curves
Analog simulation of XNets (use Advanced Analysis tools for smoke analysis on bypass components)
Read on for more details …

The Model Editor now supports all versions of IBIS for V-T curves.

Invoke Modeled.exe.

Invoke the IBIS converter from the menu Model > IBIS Translator.

Browse…
- 6 Oct 2013
System, PCB, & Package Design : Take Notes During Your Packaging Design Workflow with the Database Diary

Jeff Gallagher

In this blog, we take a look, not at a new command, but instead at a classic command that many of you may not even realize is in the tool today: the database diary. The database diary tool (Tools -> Database Diary...) is available in all AP...
- 3 Oct 2013
Verification: Slow Winter or New Spring for Hardware Design?

Jack Erickson

If you're looking for an entertaining gonzo take on the history and current state of hardware design, I highly recommend "The Slow Winter" by James Mickens, the "Galactic Viceroy of Research Excellence" at Microsoft.The premis...
- 3 Oct 2013
System, PCB, & Package Design : What's Good About Capture’s Update Cache? 16.6 Has a Few Enhancements!

Jerry GenPart

The 16.6 OrCad Capture release now allows you to replace multiple cache parts in one operation. In addition, all options of Replace Cache now work on Update Cache.

Read on for more details…

In earlier releases, you could not use the options available under “Replace Cache” for “Update Cache” operations. You now have the option to select multiple parts in cache and replace them in one operation:…
- 3 Oct 2013
SoC and IP: TSMC 28HPM – Sweet Spot for Today’s Mobile SoCs

Jacek Duda

Mobile is the only business besides PCs where actual SoCs get a lot of visibility in the eyes of the end customer. Does Joe Doe care what’s inside his MP3 player or car infotainment system? No, not as long as it’s doing its job. But when it comes to his smartphone or a tablet, his awareness of the chip inside is much higher.
It’s good for the business, because this awareness helps IP providers promote…
- 2 Oct 2013
SoC and IP: Automotive Ethernet Interest Soars at Industry Events

ArthurM

I attended two consecutive automotive Ethernet events near Stuttgart last week. Judging by the level of participation automotive Ethernet is really taking off.
The first event was the OPEN Alliance face-to-face meeting which 150 people attended. The main purpose of the OPEN Alliance is to promote standards for the operation of 100M and 1G Ethernet PHYs over a single twisted pair (STP) of copper cable in automotive environments…
- 1 Oct 2013
System, PCB, & Package Design : Customer Support Recommended - Dimensioning in Allegro PCB Editor

Naveen

Allegro PCB Editor offers drafting and dimensioning features that support electronic design automation (EDA) industry standards that enable you to specify the dimensions of every feature on a board created from the product. This feature gives you greater control over the manufacturing release of your design. The layout editor also enables you to customize the dimensioning process to conform to the manufacturing requirements…
- 30 Sep 2013
System, PCB, & Package Design : What's Good About ADW’s Pull-Down Lists? 16.6 Has a Few New Enhancements!

Jerry GenPart

The 16.6 Allegro Design Workbench (ADW) release now provides the ability to customize the pull-down list values for part property editing. Some classification properties require “freeform” values (tolerance, voltage, etc.) and other properties only accept certain values, for example:
“YES/NO”
“COMPLIANT/NON-COMPLIANT”

This feature allows you to specify a set of allowable values for a property…
- 24 Sep 2013
SoC and IP: Intel Developer Forum (IDF13): A "Look Inside" the Technology Showcase

Arif Khan

The recent Intel Developer Forum 2013 in San Francisco was notable for the sheer number of attendees and the broad spectrum of the technology industry they represented.
Intel's embrace of a more diversified computing ecosystem was on display -- Android mascots, tablets, and phones, and yes, servers and cloud software. Intel led the PC revolution with its x86 family of processors, but faces intense competition in the handheld…
- 23 Sep 2013
SoC and IP: IEEE 802.3 -- Standardizing the Next Generation of Ethernet PHYs

ArthurM

I attended the IEEE 802.3 standards meeting in York, England recently. Over 200 people came from all over the world to work on standards for the next generation of Ethernet products.
Work is ongoing to standardize new Ethernet PHYs (physical layer devices) for speeds of 1Gbps, 40Gbps, 100Gbps and 400Gbps. The 1Gbps work is focused on the automotive and industrial market segments, a field that Cadence is particularly committed…
- 19 Sep 2013
Digital Design: Five-Minute Tutorial: EM Model Files Revisited

Kari

Back in January, I posted a Five-Minute Tutorial about creating EM Model files. We'll be referencing this previous post a lot, so check it out quickly right now.

That method has worked well for me, but on my most recent project, I hit some snags. As process nodes evolve, the EM models are becoming more complex, and translation scripts are not able to handle all of the cases. So, I had to dig back in and find a new…
- 18 Sep 2013
Analog/Custom Design: Virtuosity: 15 Things I Learned in August by Browsing Cadence Online Support

stacyw

Our folks over in Physical Design have been busy churning out helpful Rapid Adoption Kits to demystify lots of useful features in the Virtuoso Layout Suite. It's a great opportunity to learn some new productivity-boosting tricks.
Application Notes
1. Virtuoso Spectre Transient Noise Analysis
This document discusses the theoretical background of Spectre's transient noise analysis, its implementation and implications,…
- 11 Sep 2013
System, PCB, & Package Design : What's Good About Allegro PCB Editor Shape Contraction and Expansion? Check Out 16.6!

Jerry GenPart

The 16.6 Allegro PCB Editor includes new enhancements to effectively manage shape operations.

Read on for more details …

Shape Expansion/Contraction

The ability to contract or expand an existing shape(s) is available in General Edit Application mode. Pre-select one or more shapes then use the RMB context sensitive menu to access the Expand/Contract command. Use +/- buttons in combination with the value field to incrementally…
- 10 Sep 2013
System, PCB, & Package Design : Create Optimum Pin Assignments for FPGAs on PCBs - Part 2 of 2

briggins

In part 1 of this blog, I discussed a scenario that PCB designers working with FPGA-based boards are often faced with: getting pin assignments from FPGA and/or schematic engineers that can create serious PCB routing problems. In that blog I claimed that the upstream engineers can't accurately assess the impacts of their FPGA pin selections on the PCB partially because the tools they use don't consider the PCB.…
- 6 Sep 2013

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