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SoC and IP: Embedded SSDs: SanDisk’s iSSD puts 64Gbyte SATA SSD on a BGA device measuring only 16x20mm, 1.85mm high

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The convenience of SSDs that look like HDDs is that they can seamlessly plug and bolt into the same mechanical and interface infrastructure as their mechanical brethren. Many, many embedded designs would happily forego the mechanical compatibility in exchange for a smaller volumetric requirement because many embedded systems, like nearly all mobile devices, are quite short on extra volume. That’s precisely the market…
- 23 Aug 2010
SoC and IP: Steve Wozniak talks about the importance of memory in system design

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Last week at the Flash Memory Summit, Steve Wozniak gave a keynote presentation where he strolled down memory lane, so to speak, and discussed how important memory decisions were to the development of the many systems he’s created. Memory capacity and cost strongly influence every project’s system-level design decisions and Woz’s projects are no exception. Cadence’s senior manager of technical communications Richard Goering…
- 23 Aug 2010
SoC and IP: SSDs versus HDDs: Comments on that giant, yellow, flashing, caution light

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A couple of weeks ago, I noted the continued disparity between SSD and HDD pricing in a local advertiser’s newspaper ad and got several interesting responses on LinkedIn. (See The differential cost between SSDs and HDDs continue in today’s Fry’s ad. Giant flashing yellow caution light for SSDs.) Here’s a particularly thought-provoking response from Dave Byrne in Swindon, UK:

"On Steve's original question with regards…
- 23 Aug 2010
Digital Design: Webinar: SOI Gives More Performance Per Watt, And There's An Easy Path

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If you've seen any of the recent buzz lately around Silicon-On-Insulator (SOI), you'd know that it's an excellent option that can enable you to meet lower power consumption and die area targets without sacrificing performance or functionality. This is why Cadence, ARM and IBM have partnered to provide you an easy path to silicon with the SOI process for your digital design, including production proven software, design…
- 20 Aug 2010
SoC and IP: NAND Flash in Space: JPL’s Strauss reports advanced Flash devices with finer geometries better for space-borne applications

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Yesterday, I blogged about a presentation on embedded SSDs given at the Flash Memory Summit by Viking Modular Solutions during a panel on embedded Flash. Today, I want to discuss the subsequent talk on the same panel, a presentation by Karl F Strauss of NASA’s Jet Propulsion Lab (JPL). Strauss discussed the use of Flash memory for data storage in spacecraft. You might think that shrinking device geometries make newer…
- 20 Aug 2010
Verification: Inside The Virtual File System

jasona

As part of my ongoing effort to report and explain interesting topics related to Virtual Platforms, I have published a new article on the ARM DS-5 Virtual File System over at blogs.arm.com.Please head over and take a look to find out more a...
- 19 Aug 2010
SoC and IP: SSD Form Factors: Viking Modular Solutions talk at Flash Memory Summit explodes the possibilities

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Everyone “knows” what an SSD looks like. It looks just like an HDD, usually in a 2.5-inch form factor with a SATA connector. However, that’s not the only possible form factor, not by a long shot. Yesterday, at the Flash Memory Summit, Viking Modular Solution’s Flash Product Marketing Manager Steve Garceau stepped through a series of alternate form factors in a session on NAND Flash SSDs for embedded applications. I found…
- 19 Aug 2010
System, PCB, & Package Design : What's Good About Deleting Parts in ADW? You Can Easily Do This In ADW16.3!

Jerry GenPart

Part, Schematic, Footprint and Models can all be deleted from the database now with the Allegro Design Workbench ADW16.3 release. Schematic and footprint models may only be deleted if they are not associated with a part. Once a Schematic or Footprint model is deleted from the database, the model is removed from the reference library. The deleted model archive is retained in the vault so the Librarian can check out and…
- 18 Aug 2010
Analog/Custom Design: Analog Design vs. Automation -- Why Are They At Odds?

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Back in 2002 and 2003 there was a lot of talk about analog synthesis being the "next new thing" to close the productivity gap between analog and digital designers. Well, I hope you didn't hold your breath for this!

That promise failed mostly because analog design was still a custom design challenge, relying on innovation to provide differentiation in the final application. Standardizing analog design…
- 17 Aug 2010
SoC and IP: Andy Walls of IBM talks about NAND Flash for Enterprise Applications

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Just got back from a morning spent at the Flash Memory Summit. The last talk I listened to was the pre-lunch keynote from IBM’s Andy Walls, a Distinguished Engineer who has worked at IBM for 29 years and has lots to say about enterprise storage. Walls started his keynote by discussing the 4-legged stool for a great SSD strategy. The four stool legs are:

Enable Enterprise MLC (multi-level cell) NAND Flash. You do…
- 17 Aug 2010
SoC and IP: Intel’s SSD roadmap starts appearing on the Web

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Any company in the SSD business knows it must face Intel, so there’s always wide interest in knowing Intel’s plans in this arena. Over the weekend, notices of a pretty thorough chart showing Intel’s SSD roadmap for the next 18 months started to appear on several Web sites. The latest site to carry the image of Intel’s SSD roadmap slide is the IT industry’s biggest online newstip sheet, The Register.

If you seek the…
- 16 Aug 2010
SoC and IP: AgigA Tech DDR3 memory module combines SDRAM and NAND Flash for data backup on one module

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AgigA Tech, a memory-module vendor and a subsidiary of Cypress Semiconductor, has added a DDR3 module to its family of high-speed, battery-free, non-volatile SDRAM systems. These new AGIGARAM modules combine DDR3 SDRAM with NAND Flash devices on one registered DIMM. All members in the AGIGARAM product family merge NAND Flash, DRAM, and ultracapacitor power storage to create highly reliable, non-volatile memory systems…
- 13 Aug 2010
Verification: I Think, Therefore I Blog (Cogito Ergo In Araneam Scribo)

tomacadence

I realized that I have just passed the second anniversary of my first blog post, which caused me to ponder a bit about this relatively new vehicle for communication. This is fair warning: some of you may find this post to be self-indulgent piffle. If so, feel free to ignore it, but you have to swear that you've never followed any of the Twitter twits who engage in self-indulgent piffle all day, every day ("I'm driving…
- 13 Aug 2010
Verification: Ericsson Selects Specman Constrained-Random Verification To Improve Efficiency And Quality

teamspecman

Sarmad Dahir of Ericsson switched from directed testing to constrained-random test generation and the metric-driven verification (MDV) flow. Constrained-random testing is much more efficient than the old directed test approach, Dahir said. "Random testing makes things easier, because you won't have to target every possible scenario."
This translates into a time savings -- perhaps 30 percent for the overall…
- 11 Aug 2010
System, PCB, & Package Design : What's Good About DEHDL Anchor Point Wire Stretch? It's In SPB16.3!

Jerry GenPart

Just a very quick post this week on a simple, but elegant new SPB16.3 feature for the Allegro Design Entry HDL product.
Prior to the SPB16.3 release, Design Entry HDL (DEHDL) did not have the capability of drawing a new wire from an anchor point of an existing wire. Introducing the anchor point wire stretch will give an extra ease of use factor to the way the wires are connected in the schematic.

You can stretch a wire…
- 11 Aug 2010
SoC and IP: The differential cost between SSDs and HDDs continue in today’s Fry’s ad. Giant flashing yellow caution light for SSDs.

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Today’s Fry’s Electronics ad on the back page of the first section of the San Jose Mercury News carried a giant flashing yellow caution light with respect to SSD adoption. OK, so there wasn’t really a big flashing yellow caution light, after all this is still newsprint, but that’s how my mind interpreted what I saw on that back page. The Fry’s Electronics ads are ever present in the San Jose Mercury News and today’s ad…
- 11 Aug 2010
SoC and IP: Just what does “XXnm-class” mean for NAND Flash devices? Why the smoke? Why the mirrors?

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Two days ago, I posted a short blog entry on Hynix’s new “20nm-class” 64Gbit NAND Flash devices and received a couple of questions about just what “20nm-class” means. Does it mean 20nm? 29nm? 26nm? 25.5nm? What? Truth is, this is a game that all the memory vendors are starting to play to obfuscate what they’re doing while generating some news coverage. Today, I found an excellent response on Lars-Göran Nilsson’s SemiAccurate…
- 11 Aug 2010
Verification: e Templates: A Nifty Way To Create Reusable Code

teamspecman

Hi All,

An e template (known as a parameterized type in other programming languages) is a feature that has been around for several releases and can be a great way of creating re-usable code. Templates can be used anywhere a user would like to create a single re-useable object that might operate on different data types. An example would be to create a scoreboard (if you were not already using the ovm_scbd package…
- 10 Aug 2010
Digital Design: Abstracts For CDNLive! Silicon Valley 2010 Due August 22

BobD

Don't let the name CDNLive! confuse you. It's the Cadence user's group conference and for North America this year it's occurring in Silicon Valley October 26th, 2010. The conference also includes Technology Demos and a Designer Expo, but the heart of the event is really the user presentations. If you haven't submitted a paper for consideration or haven't even thought of a topic to talk about, don't worry…
- 9 Aug 2010
SoC and IP: Hynix initiates “20nm-class” NAND Flash production with 64Gbit devices

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Hynix announced yesterday that it has begun mass production of 64Gbit NAND Flash using “20nm-class” fabrication technology at its 300mm M11 fab at the company’s Cheongju site in central South Korea. The Company developed this manufacturing technology earlier this year and has been working with Israel-based Anobit, which is supplying expertise related to its Memory Signal Processing (MSP) technology. Anobit’s MSP is based…
- 9 Aug 2010
Digital Design: EDA Follow-The-Leader ... Signoff In The Design Flow

PeteMc

As a member of the EDA community, I find it interesting and somewhat frustrating to see how much we copy each other at times. Ever notice how one company might make a position on something, and once their message resonates, then a lot of other companies come out of the woodwork with me-too messaging and positioning?
I saw this happen on mixed-signal design, and now see it happening on signoff analysis.
Here at Cadence,…
- 9 Aug 2010
Verification: e Verification Job Postings We’ve Seen

teamspecman
Specmaniacs between jobs: over the last few weeks we’ve seen job postings for verification engineering in general, and e/Specman expertise in specific, in the LinkedIn groups:
“Experts in SystemVerilog/Specman/VERA/System C”
“Think Verification”
“HVL (SystemC/C++/Verilog /Vera/Specman) Experts”
While we tweet verification-related posts whenever we come across them, if you’re on LinkedIn…
- 6 Aug 2010
Verification: TLM-driven Design And Verification Methodology Book Author Interviews

Steve Brown

The recently published TLM-driven Design and Verification Methodology book has been an immediate hit, receiving critical acclaim. The authors each labored and reveled in the creation process. To give you a little insight into each author's perspe...
- 6 Aug 2010
Analog/Custom Design: Things You Didn't Know About Virtuoso: ADE XL Test Setup

stacyw

In my last post, I left you in suspense, with your mouse hovering over the words "Click to add test" in ADE XL. Clicking on this button will bring up the ADE XL Test Editor window (which should look suspiciously familiar) and a dialog asking you to point to the design you want to use. This design does not have to be the same cellview as the adexl view you're working with. It can be any design you want to…
- 5 Aug 2010
SoC and IP: Memcon 2010 proceedings now online

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Last week’s MemCon 2010 was a blowout event, focusing on the past, present, and future of DRAM. If you would like a look at the presentations and would like to hear the speakers present, you’ll find PDFs and audio recordings here.

Thanks to all of the terrific speakers and to all of the attendees who made this a very successful MemCon. We will see all of you (and more) next year!
- 5 Aug 2010

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