Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: DAC Perspective One Week Later

tomacadence

DAC in Anaheim last week was as busy as always, perhaps more so, and of course I arrived back in San Jose to a mountain of work set aside during the show and the run-up to it. But I have dug myself out enough to look back at DAC and make a few observations. First of all, I know that overall attendance was down but I was as busy as I've ever been there. Cadence was back at DAC in a big way, and there was a lot of activity…
- 25 Jun 2010
Verification: IntelliGen Moving Into The Spotlight With Pgen Deprecation

teamspecman
Specman's new Aspect Oriented Generation Engine, IntelliGen, has now been in service for several years and we have received much positive feedback from customers in terms of ease of use, solvability, coverage and performance. For more information on IntelliGen, check out the following links, as well as other blogs written in this forum.
Introducing Aspect Oriented Generation
Debugging with IntelliGen.
Customers employing…
- 25 Jun 2010
SoC and IP: Elpida, Powertech Technology, and UMC team up to mate SOCs and memory using 3D design and assembly, targeting 28nm node

archive

The idea of 3D wafer stacking isn’t new. I wrote an article about 3D assembly of silicon die and entire wafers using through-silicon vias (TSVs) more than 20 years ago in an EDN series titled Decade 90, but it was only an experimental technology way back then. Over the past 10 years, SIP or system-in-package assembly techniques have taken the compact mobile product world by storm, particularly in products such as cell…
- 24 Jun 2010
SoC and IP: SanDisk’s WORM (write-once, read mostly) SD card can’t be altered once written. Good for secure legal and medical applications. Good for everyday digital film?

archive

SanDisk has just unveiled a WORM (write-once, read mostly) variant of the ubiquitous SD Flash memory card that’s intended for applications where stored data must be tamper-proof and unalterable. Such situations include video, image, audio and other forms of legal evidence; business and tax records; voting records; and medical records. In all such cases, all parties must believe that the data is exactly as it should…
- 23 Jun 2010
System, PCB, & Package Design : What's Good About Vias And The Allegro Router? SPB16.3 Has A Few New Enhancements!

Jerry GenPart

A few new enhancements specific to vias in the SPB16.3 release of Allegro PCB Editor have been introduced. The are called use via region and stacked via support.
Use Via Region
Many times you need to restrict usage of specific vias in a region. Allegro PCB Router has been enhanced to allow via usage in a certain region.
The use_via rule has been enhanced to align with the Allegro via list functionality. The following objects…
- 22 Jun 2010
SoC and IP: MemCon 2010 Agenda. July 28, Santa Clara, California. Register Now.

archive

MemCon is coming up next month, on July 28 in Santa Clara, California. Here’s a list of presentations and panels you’ll see. But only if you register. Register here.

Memory Market Outlook
Recurring Memory: Cycle Gathers Profit Momentum after Huge 2008 - 2009 Losses Lane Mason, Memory Market Analyst

Emerging DRAM Technology: A 3D Perspective Arun Kamat, VP Marketing
Hynix

Designing High Efficiency DDR3…
- 22 Jun 2010
Verification: DAC360: Photo blog of DAC 2010 in Anaheim, CA

jvh3

Click here or on the image below to go to the annotated photo blog of DAC 2010.

Images and notes include highlights from:
* The Cadence and OVM/UVM booths
* Sites around the show floor
* Things outside of the expo, including panels, papers, and presentations (Yes, there is more to DAC than booths!)
Enjoy!
Joe Hupcey III

P.S. Some images from "Day 0" of DAC are posted here.

On Twitter: @jhupcey, http://twitter.com/j…
- 22 Jun 2010
SoC and IP: Xilinx unleashes triad of low-power, 28nm FPGA families with very promising characteristics for memory interfacing

archive

Today, Xilinx unveiled three new series of FPGAs all based on 28nm process technology from Samsung and TSMC. The three families are called the Virtex-7, Kintex-7, and Artix-7 series. All three FPGA families feature programmable I/O drivers with I/O voltages as low as 1.2V, which theoretically permits the use of all advanced, single-ended SDRAM interfaces such as the low-voltage LPDDR2 and high-speed DDR3-2133 memory interfaces…
- 21 Jun 2010
SoC and IP: ProMOS in Taiwan brings up Elpida 63nm process, successfully builds 1-Gbit DDR3 SDRAMs

archive

Taiwan DRAM maker ProMOS has just announced successful fabrication of 1-Gbit DDR3 SDRAMs using Elpida’s 63nm (a 65nm shrink) fabrication process, transferred to ProMOS under a strategic partnership between the two companies that was initiated at the end of 2009. The 63nm process is up and running at ProMOS’ Taichung fab and the first trial lot of devices meets parametrics, signifying successful transfer of the 63nm process…
- 21 Jun 2010
Verification: DAC Cabbie Taught Me All I Need to Know About Verification

Adam Sherer

Confidence from competence. Measurement through metrics. Sell without selling. These are the pearls I learned from my cab driver on the way home from DAC. Aside from the core truths they convey, they clearly define the top three verification items I saw at 47th DAC in Anaheim this year.
Topping my list is the surging interest in OVM as it matriculates into the Accellera UVM. The OVM/UVM booth at DAC picked up nearly 800…
- 21 Jun 2010
SoC and IP: Samsung’s 512 Gbyte SSD pushes SATA 3 Gbps to the limit with “30nm class” Toggle NAND Flash chips

archive

Samsung just announced that it will be in volume production with a high-speed, 512 Gbyte SSD next month. The company rates the drive’s sequential read and write performance at 250 Gbytes/sec and 220 Gbytes/sec respectively. According to Samsung, these performance numbers come from a combination of 32-Gbit toggle-mode NAND Flash chips (produced in a “30nm class” process announced at the end of 2009) and Samsung’s Flash…
- 18 Jun 2010
Verification: What's The Best Way To Reduce SoC Development Costs?

jasona

Before I got started with my DAC 2010 customer meetings on Monday morning, I stopped by the DAC Pavilion to hear what Gary Smith had to say in his "Trends and What's Hot at DAC" session. I was very pleased to hear Gary say that Virtual ...
- 16 Jun 2010
Verification: Hit The Road - DAC!

tomacadence

OK, now that the Design Automation Conference (DAC) seems to be rotating among San Francisco, San Diego, and Anaheim, there's not too much "hitting the road" for us Silicon Valley denizens. We either drive an hour north to SF or fly an hour south to SoCal. This year DAC is in Anaheim, where I've just arrived and attended a very nice opening reception.
I'll admit that I had grown a bit tired of going to…
- 13 Jun 2010
Verification: Snapshots From Day 0 of DAC 2010

jvh3

Below are some snapshots of some "day 0" events, and last minute DAC preparations.
Evidence of growing SystemC tide: it was an amazingly beautiful Sunday here in Anaheim -- perfect beach weather. However, ~50 creators & integrators were hunkered down taking notes at the NASCUG meeting.

Graphics being mounted to the Cadence booth. (Suffice to say, our booth looks really sharp this year -- I'll wait until tomorrow…
- 13 Jun 2010
Verification: Advanced Option Brings New Features to Specman/e Users

teamspecman
Great news for Specmaniacs -- a new Specman Advanced Option is being announced at the Design Automation Conference (DAC) for Specman/e users. Three key functionalities in this Option will be:
Multi-core Compilation - Close to Nx (N= # cores) speedup in compilation time.
Re-Seed/Dynamic Load - Allow users to run a simulation and/or regression run until some pivot point, save the state, and start the test from this point…
- 11 Jun 2010
SoC and IP: MemCon 2010 registration closing in on 400 attendees. Theme is "Roadmap: GHz DDR3 and Beyond"

archive

We’re still more than a month away from MemCon 2010 in Santa Clara (July 28) and the registration is closing in on 400 attendees. We expect many more than that to register and, unfortunately, the rooms have a finite size so there’s a limit to the number of registrations we can accept because there’s a limit to the number of seats we can put into the room. If you’re on the fence, still deciding, shouldn’t you just go ahead…
- 11 Jun 2010
Verification: A New Toy for UVM Geeks

Team MDV

Wasn't it great when you were a kid at Christmas, and you got all those new toys to play with? You could keep yourself entertained for weeks, and with a really good toy, maybe the whole year. As we get older, our taste in toys changes, but the effect is still the same. My latest toy is my motorcycle; I never thought I could have so much fun with just one thing. But when my day job is done, its all I think about.…
- 11 Jun 2010
SoC and IP: Questions for the DAC Pavilion Panel on multicore design

archive

As I wrote yesterday, I’ll be chairing a Multicore panel at DAC in Anaheim on Monday in the Panel Pavilion at DAC. This morning, I worked on creating some questions for the panelists with my good friend Markus Levy, President of the Multicore Association, who was the original person scheduled to be the moderator.

Here are the questions so far:

1. What comes first with multicore, the hardware or the software?

…
- 11 Jun 2010
Verification: Cadence Contributes ESL Methodology To TSMC Reference Flow 11

Steve Brown

The EDA360 industry vision document shows how growing complexity and application-driven development are requiring orders-of-magnitude improvements in design productivity. With its new Reference Flow 11, TSMC has taken an important step towards a stan...
- 11 Jun 2010
SoC and IP: Don’t miss the multicore Pavilion panel discussion at DAC on Monday, June 14

archive

I’ll be moderating the Pavilion panel titled “The Multiplier Effect: Developing Multi-Core, Multi-OS Applications” at DAC on Monday at 10:30 am. It’s no secret that ICs with multiple processor cores are now the norm rather than the exception. Yet there’s a real ad hoc feel to assembling these multicore designs. Is there a better way to develop these complex designs? Oh, yes. These multicore designs use memory like nobody…
- 10 Jun 2010
SoC and IP: Denali to demo new PureSpec 2.0 verification-management technology at DAC 2010

archive

This news is a bit far afield for Denali’s Memory Blog, but many of our blog readers are deeply involved in verification. Next week at DAC in Booth 1183, Denali will be demonstrating a huge leap forward in verification-management technology with early previews of its PureSpec 2.0 tool. Because of its leading presence in verification IP (VIP), Denali is actively involved in verification flows. Working with customers on…
- 10 Jun 2010
SoC and IP: Making SSDs, the TweakTown video: See how A-DATA makes SSDs based on SandForce SF-1222

archive

TweakTown’s crew visited A-DATA’s manufacturing floor during Computex in Taiwan and shot video of A-Data’s entire manufacturing and test process. If you haven’t seen how SSDs are manufactured, this video will give you a pretty good idea of how it’s done, what kind of machines you use, and how much manual labor a vendor like A-DATA puts into its SSDs. If you are already familiar with the SSD manufacturing process, I’d…
- 10 Jun 2010
SoC and IP: ST Microelectronics’ SPEAr1300 Embedded Processor family employs Denali Databahn DDR controller and PHY to control multiple DDR SDRAM generations

archive

Last month, this blog described the new SPEAr1300 Embedded Processor family from ST Microelectronics and focused on that chip family’s ability to control either DDR2 or DDR3 memory. Designing the ability to control multiple DDR SDRAM generations into an SOC like the SPEAr1300 is a good idea because it gives the system designers using the SOC maximum flexibility in selecting a memory technology that best fits the end product…
- 9 Jun 2010
Verification: Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing Platform

rmathur

For a while now, Cadence has been providing leading verification solutions and methodologies such as metric driven verification (MDV). MDV guides verification projects from initial planning to verification closure. Engineers need automated verific...
- 9 Jun 2010
Analog/Custom Design: ARM And Cadence Get To The “Core” Of Mixed-Signal Design

nizic

An increasing number of analog and mixed-signal designs in automotive, power management, wireless, medical, and industrial applications require digital control. But designing a state machine, and integrating the increasing amount of logic gates that implements it, has been challenging for analog designers. They often start implementing some digital functionality using a custom methodology, but soon the growing gate count…
- 8 Jun 2010

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.