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I still remember my first encounter with OCEAN. It was 2002 and my co-worker had asked me to run a simple test for him.  I sat in my cube, ruffling through our user guides, trying to quickly learn just enough to do the task at hand.  The story ended happily,  but I sure would have saved some time and frustration had I seen the following video.  So for you OCEAN neophytes out there, here’s a nutshell video to get you out of…

You've probably read about all the buzz in the EDA news this week -

"Cadence acquires FPGA-focused EDA startup" and here.

"Cadence buys Taray in time for 28nm FPGAs"

"Cadence Acquires FPGA Tool Firm Taray"

"Cadence acquires Taray (why did it take them so long?)"


Of course, the Taray "7 Circuits" FPGA optimization technology had been integrated into the Cadence OrCAD and…

In my last blog entry, I mentioned that I was able to keep up with a lot of the discussion going on at a recent Accellera TSC meeting just by reading the tweets from the participants. That experience got me thinking about how much social media has changed the nature of such meetings, and the consequences of these changes. Clearly, public tweeting from confidential meetings related to your job is crazy and an invitation…

In an earlier post Team Specman had the pleasure of introducing the free, open source software (FOSS) "CFS Vision" project.  The CFS Vision team has now posted this brief introductory video on the Java-based eVC Generator utility described in our interview with their leader, Cristian Slav:

Enjoy the video, and this free utility!

Team Specman

P.S. Do you have…

Allegro PCB SI has supported multiple simulation engines for well over seven years.  Other than the native TLsim engine, HSpice has been one of the more popular simulation engine choices.  This year at SNUG, we have been invited to meet with HSpice users and show them the value of running HSpice directly from the Cadence Allegro PCB SI environment.

This demonstration shows HSpice running with IBIS models, and compares the…

Many of our customers use our Virtuoso software in combination with the windows emulation product from OpenText named "Exceed on Demand".   To maximize performance between the two tools, we have some recommendations: 

For IC6.1.4 and Exceed on Demand 7, these setting will cause problems between the two programs.  You should change the settings to the following:

Steve Lewis

This week, I'm taking a brief break from the usual PCB solution/product technical discussions and focusing on a very interesting capability used with the Cadence Allegro PCB Editor product.

You can read all the details from this article - Integrated Optical & Electronic Interconnect PCB Manufacturing in a recent PCB007 update.

 Most of you know that my primary focus is the "front end" environment for the Cadence…

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group in the UK]

Building on the Part 1 introduction to Specman’s messaging built-in infrastructure, allow me to share some tips on how to programmatically control and scale message display to help shorten your debug time.

First and foremost: please, please, please avoid manually commenting out/in debug messages.  While it’s very tempting to…

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face-to-face meeting held last week in Massachusetts. But with the steady stream of tweets coming from several of those who did attend, I almost felt as if I were there. That experience will be subject of my next blog entry, but for today I want to touch on some of the interesting news from the face-to-face. Perhaps the most exciting was that…

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK]

Messaging is important for two main reasons:

• It is essential for debugging

• It can greatly impact simulation performance

This is why Specman has a messaging infrastructure built-in to provide an easy to use, scalable and efficient mechanism.  Furthermore, Specman’s messaging capabilities allow you to do almost anything which you can conceive…

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release

These enhancements will improve your experience with analyzing simulation results especially for dense designs.

 These features include:

• Easy to use pop-up menu for traces
• Access to Trace Property and Hide and Show Traces
• Customizing auto-rotation of trace color from an enhanced color set
• Controlling background and foreground…

Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule.   A major stumbling block that can be a real threat to that predictability is iterations between different stages of the design flow. There are multiple reasons why this happens but one that should not happen is because…

I'm not going to beat around the bush here.  I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4.  I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that a word?), undockable and tabbable (I know that's not a word, but it's fun to say) just like the assistants in the main Virtuoso window.  I could tell you that the…

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol.  Here is the official announcement, which includes AMBA4 and VIP highlights.

What this means in practical terms:

• If you have licenses for the Cadence VIP Portfolio (part number "VIP100"), you will receive…

Richard Goering's recent interview with Mitch Weaver on the future of Specman and e put me in a reflective mood about my own evolving opinions. My hands-on experience with Specman is minimal; back in my 0-In applications days I co-developed a joint demo with Verisity (prior to acquisition by Cadence) in which I had the chance to do a bit of e testbench coding. I was very familiar with formal at that point, but it…

Just a brief post this week to highlight one of the new SPB16.3 features in Allegro Design Entry CIS.

In complex designs containing a large number of parts, the task of wiring the parts together is often a time consuming and tedious task. Wiring multiple pins to a bus can also be a tedious and repetitive task. Capture now includes an Auto-Wiring feature that allows you to wire two or more pins or wires on your schematic…

Last week at DVCon, frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs".  In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like -- well, you know -- are at an inherent disadvantage vs. AOP approach (like in e) when it comes to the unique requirements of verification.

Click here if the embedded…

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence.  

A couple of months ago we came out with this great new Virtuoso software release (IC 6.1.4).  So, despite my best efforts to get you to use the recently-opened files list or to create bookmarks, the first thing you did after starting virtuoso was open the Library Manager.  (Don't try to deny it, I know you did...). 

So there's the Library…

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3.

The images and notes include highlights from:

• A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper

• The paper "Tweak Free Reuse With OVM"

• A paper on "Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCs"…