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SoC and IP: Does Samsung really scare Japan? EETimes’ Junko Yoshida thinks so.

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EETimes' Junko Yoshida just published an article titled “5 reasons why Samsung scares Japan” (http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=225200248) that discusses five major reasons why Samsung has become the manufacturing powerhouse that it is today. There’s no question that in semiconductor memory, Samsung is a true industry leader. According to DRAMeXchange, Samsung was the dominant player in semiconductor…
- 27 May 2010
SoC and IP: Marc Greenberg’s “big resistor” model of semiconductor DRAM power consumption

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Too many DRAM choices. If you want low power DRAM, do you choose LPDDR1, LPDDR2, DDR2L, DDR3L, or what? It’s not an easy choice because of all the variables involved: the peak and average transfer rates, the power supply voltages, and the IC manufacturing process technology used--just to name three. In addition there are the DRAMs’ various operating modes and the corresponding current consumption in each mode. The modes…
- 25 May 2010
SoC and IP: OCZ Enyo USB 3.0 SSD reviewed by PC Perspective video

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Earlier, we covered the announcement of OCZ’s Enyo USB 3.0 external SSD. Now PC Perspective has created a pretty interesting video review of the drive. OK, the review starts kind of slow and seems to have very little technical meat but you might want to let the video play until they disassemble the drive to reveal the product’s interesting silicon guts. That’s when you’ll learn all you need to know about the chips inside…
- 25 May 2010
SoC and IP: InfoWeek video series chronicles storage and SSD Evolution. Part 1 runs 8 minutes, 42 seconds

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Can you spare nine minutes to get a really good grounding in SSD concepts? No? How about eight minutes and forty-two seconds? Ah, now we’re talking. Information Week and with Storage Switzerland’s Lead Analyst George Crump have produced an excellent 4-part video tutorial series on SSDs. Each part runs less than 10 minutes and Part 1 covers the technical side of storage evolution in a concise and interesting way that’s…
- 25 May 2010
System, PCB, & Package Design : What's Good About Browsing For Power Pins in Capture? It's In SPB16.3!

Jerry GenPart

The SPB16.3 release of Allegro Design Entry CIS (Capture) now allows you to browse power pins in your design. In Capture, most of the design’s power pins are invisible, which makes it difficult to find power pins. The new "browse power pins" capability will help you find the pins faster and increase your productivity.
In Capture, power and ground supply pins are referred to generically as "power pins."…
- 25 May 2010
SoC and IP: Squeeze bandwidth inefficiencies out of DDR DRAMs in memory subsystem designs

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This blog starts with a simple, sad truth: DDR DRAMs are naturally inefficient. If this statement bothers you, just get over it. All human-made artifacts have inefficiencies and DRAMs are no different. However, there are things you can do to squeeze every bit of bandwidth efficiency out of a DDR DRAM and your efforts can be rewarded with significant performance gains. You can improve memory-subsystem bandwidth by 20-30…
- 24 May 2010
Digital Design: Mixed Signal: Why The Sudden Attention?

PeteMc

With DAC 2010 rapidly approaching, we can again expect that lots of EDA and IP vendors will use “mixed signal” somewhere in their company’s messaging. Last year it seemed that nearly everyone wanted to jump on the mixed signal “bandwagon” … so what caused this sudden jump in interest in mixed signal?

We all know that mixed signal design is not new. It’s been around for about 20 years (give or take), but there has…
- 24 May 2010
SoC and IP: Why is it so difficult to interface with DRAMs?

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One of the maxims in the world of system design is that it has always been relatively hard to interface with DRAMs and make them work properly in all possible operational situations. This isn’t a new situation. It’s been hard to interface with DRAMs since the day they were first introduced back in October, 1970 when Intel rolled out the first commercial DRAM, the 1-kbit 1103. Intel’s 1103 DRAM was a PMOS chip that introduced…
- 24 May 2010
Verification: The Future of OVM, VMM, and UVM

mstellfox

In my last blog, I took a look back at the history of how we got to the first delivery of UVM. Now, let's take a look forward. Over the past week since UVM was released, and Cadence opened the UVMWorld portal to support the new UVM Community and ecosystem, I have seen a number of customers asking questions about when to move to UVM as well as the future of OVM and VMM. Since my team has been developing the OVM over…
- 24 May 2010
SoC and IP: Google TV and Intel’s CE4100 SOC (Sodaville)--is this a world-beating combo or what?

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Having vacuumed up most of the world’s very large and growing Internet advertising budget and having siphoned off a substantial amount of print advertising dollars as well, Google has now clearly set its sights on yet another juicy cache of advertising dollars: broadcast, cable, and satellite television. Google rolled out Google TV yesterday as a first warning shot. The concept is a set of services and front-end consumer…
- 21 May 2010
SoC and IP: MemCon 2010, July 28: Time to Register. Hundreds already have!

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How’s your July shaping up? No, that’s not just an idle question about your future vacation plans. If you have anything to do with semiconductor memory--use it, make it, design with it, buy it, dream about it, etc--get out your calendar and reserve July 28 because that’s when MemCon 2010 takes place here in Silicon Valley. Although we’re not quite ready to post the agenda (real soon now, possibly as soon as next week…
- 21 May 2010
Verification: Tech TIP: Incisive Formal GUI Updates - Making It Easier

TeamVerify
The Incisive Formal GUI has had some recent changes made to it. You asked for the following:
Way to filter based on status and property types
Add the "Reinvoke" feature as a dedicated button
Ability to run selected properties from the GUI
and they are available in IFV/IEV version 09.20-s009 or newer.
Assertion Filter Buttons
The IFV GUI has been enhanced to provide single click filter capabilities. You can now not…
- 21 May 2010
SoC and IP: Seagate Tweet unleashes avalanche of speculation: fast gamers' 2.5-inch HDD with integrated Flash cache imminent?

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Earlier this week, Seagate sent out the following Tweet:

“Your hard drive is an extension of you. Adaptive Memory Technology. See for yourself on 5/26. http://ow.ly/1NjTD #gamers”
The link takes you to a sign-up page for an online event to be held on May 26 when Seagate will be rolling out a new product. The page also contains the image of what’s obviously a hard disk drive mostly under wraps. Imagine that, Seagate…
- 20 May 2010
System, PCB, & Package Design : Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export File Formats

TeamAllegro

This is the second in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool.Recently on a visit to an avid user of IC Package design tools, we heard the requirement ma...
- 20 May 2010
SoC and IP: LPDDR2: The new mainstream memory for embedded and mobile applications?

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Yesterday, ST-Ericsson announced a new smartphone platform called the U8500 which employs a Denali Databahn SDRAM controller and STMicroelectronics’ DFI-compliant Physical IP (PHY) and state-of the-art 1.2V LPDDR2 Input/Output pads to control off-chip LPDDR2 DRAM (see First Silicon Success With LPDDR2 SDRAM Controller IP For High-Performance, Low-Power SoC). While DDR3 memory is starting to become the mainstream SDRAM…
- 20 May 2010
RF Engineering: New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA!

Tawna

If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes troubleshooting circuits containing nports (s-parameters ) much easier and faster!
Starting in IC6.1.4 ISR2, you can now plot s-parameters directly in ViVA (without having...
- 20 May 2010
System, PCB, & Package Design : What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release!

Jerry GenPart
The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features to the part and model status capabilities.

As a part moves through its part lifecycle, ADW provides the ability to control how that part behaves.

These new features include:
A “Development” status for library development operations
Part lifecycle for business operations
Ability to define behavior based on part’s lifecycle…
- 20 May 2010
SoC and IP: Party on at DAC, says Denali

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Back by popular demand, the Denali DAC party. The big one. With the bells and whistles. With the idol contest. The one with the outrageous and copious quantities of music and fun. Oh yeah, and copious amounts of alcoholic beverages. That one.

Want to go? It’s all on you. To get a ticket, you’re gonna’ need to register here: http://a.denali.com/4H. Then you need to get to Denali’s booth first thing Monday morning at…
- 18 May 2010
RF Engineering: Using RF Simulation Technology for Analog Applications

Hany

The particular nature of analog circuits puts restrictive requirements on circuit simulators. The EDA industry has introduced proven shortcuts to deliver simulation speed and accuracy for specific applications, e.g. Harmonic Balance for RF and partitioning...
- 18 May 2010
Verification: UVM World Community Site Now Available!

tomacadence

Yesterday morning, the verification world was buzzing with the first release of the Universal Verification Methodology (UVM) standard library and documentation from Accellera. This represents a major milestone for Accellera as well as for the EDA industry, since it is the first time that all the major verification vendors have aligned on a single methodology.
Yesterday afternoon, Cadence followed up the Accellera release…
- 18 May 2010
SoC and IP: 1.8-inch SSD with PATA interface targets mini Notebooks, Netbooks, good for embedded apps too

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With all of the recent SSD announcements, you might think that the only form factor and interface for an SSD would be 2.5 inches and SATA. This blog has covered some other SSD advances such as SSDs with PCIe interfaces at the high end, but there’s another end to consider. Many Netbooks and mini Notebooks still have IDE/PATA interfaces and employ 1.8-inch HDDs. Further, many, many embedded systems have the older IDE/PATA…
- 18 May 2010
Verification: UVM - 10 Years in the Making ...

mstellfox

In case you the missed the news today, the Accellera VIP TSC released the first version of the Universal Verification Methodology (UVM). This represents a significant achievement on the part of the TSC as it is the first standard SystemVerilog Base-Class Library and Methodology. While there has been a lot of hard work by many members of the TSC since December of last year when the OVM was chosen to be the basis of the UVM…
- 17 May 2010
SoC and IP: Toshiba stands on 2Xnm NAND platform with devices, SSDs, and hybrid storage

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Last week, Toshiba’s president and CEO Norio Sasaki stood firmly upon a leading-edge NAND Flash technology platform as he discussed his company’s future plans for memory and storage development, as reported by Nikkei Business Publications’ Tech-On!. Sasaki said that Toshiba plans to move forward with 2Xnm Flash processing by this summer, having already achieved volume production of 32nm NAND Flash devices in March. Sasaki…
- 17 May 2010
Verification: Initial Release of the UVM Now Available!

tomacadence

As Richard Goering just reported, the Accellera VIP Technical Subcommittee (TSC) this morning posted the first release of the Universal Verification Methodology (UVM), tagged "1.0 Early Adopter" since there is a bit of new technology beyond the OVM 2.1.1 baseline. This is great news for the verification community; at last we have a single library and methodology around which we can rally.
I've been somewhat of…
- 17 May 2010
System, PCB, & Package Design : DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

TeamAllegro

Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages, programmable ODT, derating tables, write leveling, and on and on.
Fortunately, the folks working on…
- 17 May 2010

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