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We recently announced the 9.1 version of the Encounter Digital Implementation System.  Head over to http://downloads.cadence.com, select your platform and choose EDI91.  Notice that in our download system, we’re calling it EDI as opposed to the former SOC to align with a name change from SoC-Encounter to EDI System that occurred in the 8.1 release.

I think customers will be interested in three high-level aspects of…

A new year means another DesignCon and 2010 is an exciting year for the PCB and IC Packaging team at Cadence – sometimes known as TeamAllegro.

This year you will find the Cadence booth at an ideal location in the center of the Exhibition floor.  We will have a demo pod dedicated to Allegro and SiP.  We’ll be happy to show you the latest technology around multi-gigabit, DDR3, and power integrity as it works seamlessly…

Design teams have used C/C++/SystemC reference models for many years and the trend is growing with SystemC synthesis.  At the same time, many teams are adding power-aware structures to their designs and trying to simulate.  So what happens when the models encounter unknowns propagated from shutdown  blocks?

For the unprepared, the simulation fails.  In most cases. the models were written before low-power simulations were…

Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against the main verification technology-specific observations that I saw throughout the year.

Prediction 1: all of the following would become more intense:

1. 1 billion logic gate…

In the SPB16.3 release, the SiP Layout Assembly Design Rules Checker (ADRC) User Interface has been integrated with the Constraint Manager will thereby become consistent with other design rule checks that use Constraint Manager technology.  This also means that exporting the technology file from SiP Layout will save the Assembly Rule constraints to the Allegro technology file for reuse in other designs. 

Terminology

In the numerous tweets, blog posts, and online forum discussions on the upcoming Universal Verification Methodology (UVM) standard from Accellera, I have seen a couple of references along the lines of "UVM=OVM+VMM" and that really concerns me. It concerns me because it's not accurate, but it concerns me even more because the very idea doesn't make sense.

Note that the Accellera decision was specifically…

By Steve Leibson for Denali Software

The appearance of SSDs into the storage arena is rapidly altering the way large-scale, enterprise-class storage systems are built. Gartner Principal Analyst Sergis Mushell discussed some of these changes at the recent Storage Visions 2010 conference held in LasVegas. Mushell focused on how the introduction of SSDs into the enterprise-class storage device market was reshaping foundation…

By Steve Leibson for Denali Software

IDC’s Research Director John Rydning and Micron’s Director of SSD Marketing Justin Sykes tackled the merging abilities of fast enterprise-class SSDs and evolving disk interface standards, particularly SATA 6G (also called SATA 6.0) and USB 3.0, while speaking on a panel about the technology of storage during the Storage Visions 2010 conference held early this year in Las Vegas…

If you’re waiting for solid-state drives (SSDs) to overtake hard-disk drives (HDDs) as the storage device of choice in computers, servers, and consumer devices then Objective Analysis’ Jim Handy has a message for you: It’s not happening any time soon. Handy’s been following storage trends for many years. He’s tracked the pricing trends of HDDs for a while and SSDs for their short…

The popularity of OVM that made it the idea choice for Accellera's UVM is rooted in it's uniquely scalable architecture.  Today's announcement by Mitsubishi Electric and the OVM Advanced Topics tutorial at DVCon are examples of scalability beyond the common SystemVerilog testbench.

For some verification teams, jumping head-first into the maw of object-oriented programming is daunting.  Object-oriented programming…

Recently, I got involved in helping out a customer who had become frustrated using the "stretch" command in the Virtuoso Schematic Editor.  They were posing all kinds of detailed questions about the different options to the command. 

Options?  The stretch command has options?  You just grab the stuff you want to stretch, select the command, and then you...well, then you stretch.  Oh, wait a minute, I remember now…

TeamMDV:  Have you ever wondered why EDA Vendors don't make it easier for our customers to learn new techniques and methodologies, or at least provide a solid reference flow to try out new releases of the tools or to be able to compare releases on the same flow?  Well, hold on,  TeamMDV is pleased to tell you about something Incisive has had for a while now to accelerate methodology and tool changes, and its called the…

Did you know that you can wave Specman objects in IES-XL *and* also save the wave setup for automatically restarting the simulation? If not, this tech tip is for you! Here is the process:

Step 0 – Once you are happy with your waveform setup, don’t forget the basic step of saving your mix of RTL signals and Specman fields/events using the [File] → [Save] command script menu item in SimVision.

By Steve Leibson for Denali Software

Today, NAND Flash is king of the semiconductor memories in terms of cost per bit, a position it has held since 2004 or 2005. Consequently, NAND Flash serves as the technology driver for semiconductor processing--a position previously held by DRAM, processors, and FPGAs. The top NAND Flash semiconductor vendors are currently fabricating NAND Flash memories using 3x nm lithography…

The Encounter Digital Implementation System offers interactive wire editing capabilities via the Wire Editor.  This is one part of the tool that becomes much easier to use with the help of a few bindkeys.  In particular, I find the "Shift-S" bindkey useful in conjunction with "Auto Query" mode becuase it provides a way to populate the Edit Route form with net name, layer, width, and spacing depending on the object you're…

The SPB16.3 SigXP UI has been enhanced to focus on giving users better access to information already available in SigXp, reducing the number of steps needed to accomplish simple tasks, provide functionality that enable easy data manipulation and provide better setup and default for an improved out of the box user experience.

In addition to those enhancements, a new layer stack approach has been added to SigXp, similar…

Good news! A long-standing source of irritation for Encounter users has been addressed in our 8.1.USR1 release.  You might not have noticed it if you've grown accustomed to backslash-escaping square brackets in object names.

For example:
selectNet DTMF_INST/RESULTS_CONV_INST/nbus_544[0]

In 7.1, if you tried to select a net with this syntax you'd get the following as the TCL interpreter treated the contents within the…

Say you have a design with 4 input frequencies: 3164M (vco), 1449M (tone0), 1456M (tone1), 1442M (tone2). Currently when you do a qpss analysis, you are inserting a total of 4 separate ports in your schematic and running a simulation.   There is a divide...

By Steve Leibson for Denali Software

If you spend a lot of time reading and thinking about solid-state drives (SSDs), you may have gotten the impression that NAND Flash storage is at odds with hard-disk storage--that it's a winner-take-all situation. In his keynote at last week's pre-CES Storage Visions 2010 conference in Las Vegas, storage analyst Tom Coughlin dispelled that notion with some cogent slides and some…

Talk about unsung -- tech writers just don't get the credit they deserve.  They sit between R&D, customers, and support trying to capture the capabilities and intent of the software and present it accurately and succintly.  They record the "tribal knowledge" of the team so that new and existing users can function at their best, but then they hear that no one has read the f****** manual.

Well one of our…

Hi, I'm Thibault Alix and I have been working with the VLM team for two years. I'm going to present what's new in Virtuoso IC6.1.4.

Cadence® Virtuoso® Layout Migrate is the physical layout migration tool within the Cadence Virtuoso custom design environment. It supports fast process and design rule migration of hard IP, custom digital designs, mixed-signal blocks, memories, and standard cell libraries…

The Open Verification Component (OVC) defined by the official OVM User Guide in the OVM downloads enables the highest levels of reuse.  While the OVM class libraries have the supporting classes for the OVC built-in, writing OVCs properly sits on the shoulders of the verification engineer.  With Amiq's DVT, the verification engineer has the means to check their OVC for OVM compliance.

To help you learn more about DVT…