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Verification: Initial Release of the UVM Now Available!

tomacadence

As Richard Goering just reported, the Accellera VIP Technical Subcommittee (TSC) this morning posted the first release of the Universal Verification Methodology (UVM), tagged "1.0 Early Adopter" since there is a bit of new technology beyond the OVM 2.1.1 baseline. This is great news for the verification community; at last we have a single library and methodology around which we can rally.
I've been somewhat of…
- 17 May 2010
System, PCB, & Package Design : DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

TeamAllegro

Last year, TimingDesigner improved the interface to PCB SI and many of our joint customers have taken advantage of performing static timing analysis on their fully routed boards using the two tools together. However, DDR3 adds a whole ’nother level of complexity with its faster speeds, lower voltages, programmable ODT, derating tables, write leveling, and on and on.
Fortunately, the folks working on…
- 17 May 2010
SoC and IP: Early Adopter release of UVM now available

archive

Accellera has been working on a new industry-standard verification methodology called the UVM (Universal Verification Methodology) and an Early Adopter release is now available here if you wish to start using the UVM today. The UVM distribution kit contains a User Guide, a Reference Manual, and an open-source reference implementation of the work completed to date. Mentor’s Dennis Brophy wrote a blog last month that said…
- 17 May 2010
Verification: EDA360: Cool People Creating Cool Stuff

jasona

Now that we have had some time to reflect on the meaning of EDA360, it occurred to me that one of the goals of EDA360 is to make EDA cool (or cooler than it already is). One way to do this is to contribute to the cool parts of products people see, li...
- 14 May 2010
Digital Design: What you didn’t know about DFM for advanced node designs: “In-route” is insufficient

Manoj Chacko

Recently, there has been a lot of buzz about addressing DFM issues during routing. This is not a surprise as the economics of increased development cost of advanced process nodes and manufacturing has influenced dramatic changes to business models of several semiconductor companies. Due to the increasing design cost and time-to-market pressure, a re-design or few weeks delay, because of poor yield for example, may mean…
- 14 May 2010
SoC and IP: SSDs in embedded control: cold rolling steel in old European factories

archive

By far, most application stories connected with SSDs revolve around servers and PCs. There’s a vast, hidden market in embedded industrial controls, where PC-like process controllers manage large machinery on a daily basis. Decades ago, these process controllers were simple state machines. In fact, they started as relay-based devices. Now, of course, they’re all processor-based. An article that appeared this week on the…
- 14 May 2010
SoC and IP: CADENCE TO ACQUIRE DENALI

archive

Complementary Transaction Supports Cadence’s EDA360 Vision
SAN JOSE and SUNNYVALE, Calif. -- May 13, 2010 -- Cadence Design Systems, Inc. (Nasdaq: CDNS), a leader in global electronic design innovation, and Denali Software, Inc., a leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that the companies have entered into a definitive merger agreement under which…
- 13 May 2010
System, PCB, & Package Design : Economic Recovery on the Way to the Airport

Team OrCAD

Last week, one of the members of TEAMOrCAD took a trip to China. The ride to the airport was provided by one of the local airport transportation service companies. In the course of talking with the driver on their way to the airport, Kevin (the driver) mentioned that the company was in the process of re-hiring drivers as business had been picking back up over the last many months; mainly experiencing an increase in business…
- 13 May 2010
SoC and IP: Mass marketing methods come to SSDs

archive

Newly introduced and available for pre-availability orders, the privately branded 2.5-inch SSDs from established Apple Mac component vendor OWC (Other World Computing) are a sign of the rapidly changing SSD landscape with respect to mass marketing of solid-state drives to end users. The Mercury Extreme Pro series of SSDs range in capacity from 50 to 480 Gbytes and they physically look pretty much like every other SSD…
- 12 May 2010
System, PCB, & Package Design : What's Good About SCM and Packageable Schematics? The Secret's in the SPB16.3 Release!

Jerry GenPart

Many customers want to use System Connectivity Manager (SCM) known as Allegro System Architect (ASA) for quick prototyping and then start using the traditional schematic based PCB design flow. Now with the Export Schematic feature available in the SPB16.3 release, you can use System Connectivity Manager to quickly capture design logic, especially for high pin-count devices and its associated connectivity, and then generate…
- 12 May 2010
SoC and IP: Enterprise-class HDDs due to disappear, soon. All hail the enterprise-class SSD.

archive

The great Grand Poobah of SSD research Jim Handy released an industry report on Enterprise SSDs last month. Enterprise applications are currently where SSDs really shine because enterprise users can translate time into money far more easily than can clients running PCs and laptops. Because SSD speed improvements are so easy to justify in terms of total cost of ownership, SSDs are quickly finding welcome spots in all manner…
- 10 May 2010
SoC and IP: Last call for free DAC tix

archive

The DAC 2010 (DAC47) free exhibit passes program has been a big success with more than 1000 free exhibit passes already claimed. If you’re procrastinating, ask yourself “Why haven’t I signed up for a free exhibit pass yet? Is there really a zero-percent chance that I’m going to DAC?”

If there is zero chance you’re going to DAC and you’re in the business of designing ICs, then you’d better ask yourself another couple…
- 10 May 2010
Verification: Inside Cadence: Training for EDA360

jvh3

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications Engineers (AEs), Services Engineers, and many Customer Support staff, have been brought together for detailed methodology and product training. The objectives of this ambitious undertaking are to bring their skills up to date, brief them on all the roadmaps, and in general prepare them for the challenges expected in the coming…
- 6 May 2010
Verification: FMCAD Call for Papers Extended to May 12

TeamVerify

Team Verify would like to inform you about the final call for papers for FMCAD 2010 (Formal Methods in Computer-Aided Design), being held 20-23 October 2010 in Lugano, Switzerland.
This conference has traditionally focused on research on formal methods in academia and industry. However, this year the conference is expanding to bridge the gap between research and real world applications, supported by a whole new "industrial…
- 6 May 2010
SoC and IP: SSDs don’t need disk interfaces. Case in point: OCZ’s USB 3.0 SuperSpeed Enyo

archive

Most SSDs are designed to be interface- and form-factor-compatible with existing rotating mass storage devices (aka: hard drives or HDDs). However, that need not be the case. Many SSD vendors are making significant sales by offering SSDs with alternate interfaces. Fusionio’s SSDs are based on PCIe for example. Perhaps the SSDs with the highest unit volume are lowly USB sticks, although their performance leaves a lot to…
- 6 May 2010
SoC and IP: New White Paper discusses the challenges of chip design based on AMBA 4

archive

ARM’s series of AMBA specifications have become a de facto standard for SoC (system-on-chip) interconnects. ARM introduced the first version of the specification more than 15 years ago and has now released the latest version of the specification, called AMBA 4. The AMBA 4 specification is actually a collection of specifications (including AXI4, AXI4-Lite, and AXI4-Streaming) that may well revolutionize the future of high…
- 5 May 2010
SoC and IP: Memory Market Outlook for 2010: How Bad (or Good) is it?

archive

If you’ve been following the roller-coaster ride that constitutes the global semiconductor memory market, then you’re probably looking over the shoulders of as many memory analysts as possible, trying to find one whose crystal ball isn’t cracked, fused, melted, or blackened. Memory analyst Lane Mason recently spent some time at Denali Software and recorded a Webcast with his overview of recent events in the global memory…
- 5 May 2010
System, PCB, & Package Design : What's Good About DEHDL Alignment? You’ve got it in the SPB16.3 Release!

Jerry GenPart

Schematic construction requires a lot of effort in placing components, wires and text/notes in such a way that the end schematic looks neatly organized. Aligning and distributing objects on a schematic can be time-consuming if it has to be done manually.
The Alignment and Distribution functionality provided in the SPB16.3 Allegro Design Entry HDL (DEHDL) product helps in speeding up the design entry process by easing the…
- 5 May 2010
Verification: Informative Tweets on WHEN Inheritance

teamspecman

Earlier today a lively and very instructive thread on the relative virtues of WHEN Inheritance developed on Twitter between @pmarriott (a D&V consultant in Montreal, Canada), @yaron_think_ver (a verification consultant based in Israel), and @teamspecman.
Because this exchange was very technical -- hence, beneficial to Specmaniacs -- for those of you not yet on Twitter allow us to replicate the thread here, plus address…
- 4 May 2010
Verification: What Does EDA360 Mean for Verification Engineers?

tomacadence

I trust that most of you have seen the recent flurry of blog posts and articles about the new Cadence "EDA360" vision. I was working on a blog entry on how this links to my world of verification when I saw my colleague Jack Erikson post "What Does EDA360 Mean for Logic Designers?" Since I liked his title, I've stolen borrowed and adapted it for my own purposes. This is by no means the final word…
- 3 May 2010
Verification: System Realization activities at CDNLive! EMEA this week

Steve Brown

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about Cadence’ offerings to address the productivity gap in Systems Realization. Here are the System Realization activities, customer presentations, and Cadence present...
- 3 May 2010
SoC and IP: Magnetic nanodot materials breakthrough presages high-density MRAM--possible competition for DRAM and Flash in five years or so?

archive

From North Carolina State University (NCSU) comes news of a materials breakthrough that promises extreme density for magnetic RAM (MRAM) devices, possibly in as little as five years or so. Dr. Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NCSU, presented a paper last month at the spring meeting of the Materials Research Society (MRS) detailing his team’s success in…
- 3 May 2010
SoC and IP: More free DAC exhibit tix; One more chance to win an Apple iPad

archive

A bit more than a week ago, this blog carried the news that you could get a free exhibit pass to the upcoming DAC in Anaheim if you work for a semiconductor company, OEM, or a system or service provider in the electronics industry (as long as your company isn’t a DAC exhibitor this year). You are also eligible for a free exhibit pass if you’re out of work and are looking for a new position. The first 500 people to sign…
- 3 May 2010
SoC and IP: Samsung announces imminent release of a multichip module integrating DRAM and PCM for Smartphone applications

archive

Hot on the heels of Numonyx’ announcement of two commercial PCM (phase-change memory) products (see “Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available in volume”), Samsung announced on April 28 that it plans to ship a device “later this quarter” that integrates DRAM and PCM devices into a multichip package (MCP). Samsung has named its flavor of PCM “PRAM” for “Phase-change RAM.” The PRAM…
- 3 May 2010
Verification: See You at CDNLive! EMEA

jasona

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big event. I'm happy to report that in addition to the top notch people mentioned there, the entire ISX team will be in attendance! As is the case every ye...
- 30 Apr 2010

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