Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

Verification: See You at CDNLive! EMEA

jasona

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big event. I'm happy to report that in addition to the top notch people mentioned there, the entire ISX team will be in attendance! As is the case every ye...
- 30 Apr 2010
Verification: 2010 CDNLive Munich Guide for Specmaniacs

teamspecman

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive! event in Munich. An overview of the conference with info on how to register is here: http://www.cadence.com/cdnlive/eu/2010/pages/agenda.aspx
Even better (from a Specmaniac perspective), none other than e/Specman co-creator Yoav Hollander will be at the event, along with verification guru Mike Stellfox. Also be sure to meet the newest…
- 30 Apr 2010
Verification: Team Verify's 2010 CDNLive Munich Guide

TeamVerify

We're excited to report that next week's annual CDNLive! event in Munich will feature many papers of interest to end-users of Incisive Formal Verifier ("IFV"), Incisive Enterprise Verifier ("IEV"), or anyone interested in either "pure formal" verification, integrated formal analysis and simulation verification, and assertion-based verification (“ABV”).
An overview of the conference…
- 29 Apr 2010
System, PCB, & Package Design : What's Good About APD’s Super Smooth Routing? See for yourself in the SPB16.3 Release!

Jerry GenPart

When using the point-to-point routing in the packaging products (APD and SIP), customers spend a significant amount of their efforts to clean up the traces after routing. The “Custom Smooth” function provides this capability, but a separate step is needed. In the SPB16.3 release, the new option - “Super Smooth” - in the smooth options of several GUI forms for the Add Connect and Slide will facilitate this process.

What…
- 29 Apr 2010
Verification: Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

Adam Sherer

More and more often it takes a village to achieve verification success. As reported recently by MathWorks, Harris pulled together technology and support from Cadence, MathWorks, and Xilinx to cut their verification time by more than 85% and achieve a defect-free FPGA implementation.
“EDA Simulator Link provided a direct co-simulation interface between our MATLAB model and our logic simulator, which enabled us to verify…
- 29 Apr 2010
SoC and IP: NAND Flash as the media killer: Sony to kill the floppy in Japan, finally

archive

Sometimes it takes decades but NAND Flash semiconductor memory is turning out to be quite the media killer. Over the last decade, NAND Flash memory has killed off 35mm photographic film for all but the most dedicated still-photography enthusiasts. With the advent of dSLR (digital single-lens reflex) cameras that also shoot video, such as the Canon 5D and 7D dSLRs, NAND Flash memory now seriously threatens to replace photographic…
- 28 Apr 2010
System, PCB, & Package Design : Favorite Features of an IC Package Designer: Flexible 3D Viewing

TeamAllegro

This is the first in a series of discussions we would like to open up regarding “favorite features” in an IC Packaging implementation design tool. We talk to customers all the time that are designing IC packages with stacked die. While t...
- 28 Apr 2010
Verification: Verified by e/Specman: The Palladium XP Verification Computing Platform

teamspecman

After much anticipation, it feels great to be free to proclaim that e/Specman (as part of IES-XL) was used with a complete, vPlan-based, metric-driven verification flow to verify the primary chips inside the new Palladium XP Verification Computing platform.

In a future post we’ll share with you some interviews with our colleagues in R&D that did this verification work, as well as how the machines in this new product line…
- 27 Apr 2010
SoC and IP: Corsair Video vividly shows SSD speedup on laptop

archive

Wondering whether an SSD really makes that much difference to laptop performance? Wonder no longer. Corsair has posted the following video that graphically illustrates how much faster boot and application loading times are when there’s an SSD present. This video should leave no doubt in your mind. In particular, watch as the video has to speed up while the HDD-equipped laptop is doing pretty much nothing.

[video…
- 26 Apr 2010
Digital Design: Hands Up, Anyone Believe That Toyota's Problems Are All Physical?

PeteMc

In the past number of weeks/months we have all seen how Toyota has struggled to manage perception around their "sudden acceleration" problems. The first fix that was proposed was a replacement of the floor mats, under the argument that the mats had been forcing the gas pedal down. Quickly following this first "solution", Toyota announced that they were issuing a recall to fix the mechanics of the gas pedal, adding…
- 26 Apr 2010
Verification: Ubuntu on ARM is Growing

jasona

Based on the title, you probably guessed I'm talking about growing in popularity. Yes, Ubuntu on ARM is growing in popularity, but here I'm referring to growing in size.About a month ago I talked to a very sharp engineer from Canonical, the m...
- 23 Apr 2010
System, PCB, & Package Design : Who’s up for Chinese?

Team OrCAD

Recently, someone asked me "...why bother translating OrCAD products to Chinese? Everyone speaks English anyway..." In a great many cases, that's probably a true statement. But if you're a Chinese engineer, what a pain it must be working with schematic and simulation tools and having to do the mental-math all day long while trying to get your job done. I did agree, though, if you've been in the industry…
- 23 Apr 2010
SoC and IP: What is a Flash cache?

archive

A Flash cache acts like SRAM memory caches that are designed to speed up DRAM access times; Flash caches speed access to HDDs in an analogous manner. Data is drawn from HDDs as needed and the retrieved data is cached in NAND Flash. The next time this data is needed, it’s drawn directly from the cache instead of the slower HDD. Flash caches do not require as much NAND Flash memory as SSDs, and therefore cost less, but…
- 23 Apr 2010
SoC and IP: Free DAC Tix -- Better hurry ‘cause they’re going fast

archive

Love DAC? Design chips? Looking for a job? Today’s your lucky day. Denali, Atrenta, and SpringSoft want you to be able to attend DAC in Anaheim (We’re going to Disneyland!) so much that they’re willing to spring for a free exhibit pass for you. All you need to do is get your carcass down to the Anaheim convention center for the event. The exhibits are open June 14-16. The rules are simple:

1. The recipient must be…
- 23 Apr 2010
SoC and IP: Numonyx 128-Mbit serial- and parallel-I/O PCM non-volatile memories now available in volume

archive

Numonyx has announced or reannounced two 128-Mbit non-volatilve memory devices based on the company’s 90nm PCM (phase change memory) process technology. These two devices target existing NOR Flash memory sockets and the company’s press release claims that both products are available now in production quantities. The two announced PCM memory devices are the Omneo P8P PCM parallel-I/O memory and the Omneo P5Q PCM serial…
- 22 Apr 2010
System, PCB, & Package Design : What's Good About Simplifying the Use of Third-Party SI Models? It's in SPB16.3!

Jerry GenPart

Today, many users receive SI models that are not in DML format. They are given IBIS models, HSpice models, Spectre models as well as other generic SPICE models. We currently provide methods for translating these model formats into DML, but it's often not straightforward. It usually requires running a batch command with options that are not familiar to the non-expert user.

This translation process has been simplified…
- 21 Apr 2010
Verification: UVM Based on OVM 2.1.1: What a Great Idea!

tomacadence

Regular readers know that I have been urging the Accellera VIP TSC to base its Universal Verification Methodology (UVM) on the OVM 2.1 release rather than on OVM 2.0.3 as voted back in December. A few readers took me to task for my shameless advocacy, suggesting that I shut up and "let the committee do its job" in a technical world unsullied by Marketing considerations. In response, I argued that successful standards…
- 21 Apr 2010
Verification: When Less Is More, Part 3: Is e code really “infinitely” more compact than SystemVerilog?

teamspecman

Building on the packet generation example of part 1, and the coverage examples of part 2 that compare the ratio of lines e code to lines of SystemVerilog for a given task, in this post I’m going to show you how to “divide by 0” and leverage e capabilities that simply don’t exist in SystemVerilog, technically making e infinitely more capable (pardon the pun – couldn’t resist).
From the beginning, the e language was designed…
- 21 Apr 2010
SoC and IP: Intel’s Atom-based Tunnel Creek SOC with integrated PCIe interface opens new era for embedded developers

Denali Blog

One of the most ignored Intel announcements of recent memory must be Doug Davis’ early disclosure at IDF (China) on April 14 (see the hour-long keynote video here) of the company’s new Atom-based Tunnel Creek, an SOC specifically designed for embedded applications. Intel’s Atom processor, a relatively low-powered implementation of the “Intel Architecture,” has been taking the low-end notebook and netbook world by storm…
- 19 Apr 2010
SoC and IP: Network World SSD Smackdown shows Fusionio’s PCIe-based SSD provides highest throughput

archive

Network World has just posted an SSD comparison test written by Logan G. Harbaugh. The test pitted some consumer-class SSDs against enterprise-class SSDs and with an Adaptec ASR5805/512 SSD controller and MaxIQ kit, which uses an attached SSD to accelerate attached drives arrays via flash caching. Overall, Harbaugh found that the SSDs improved system performance by a factor of 2 to 10 depending on the product.

The…
- 19 Apr 2010
SoC and IP: Firmware as the performance differentiator for SSD controllers

archive

Anandtech has just posted a meaty article about SandForce SSD controllers as used in SSDs from OCZ and Corsair. (Understanding SandForce's SF-1200 & SF-1500, Not All Drives are Equal) It’s worth a read from at least two perspectives. First, it gives you some pretty deep insight into the real importance and value of the firmware running on these SSD controllers. As the Anandtech article discusses, controller firmware…
- 16 Apr 2010
Digital Design: EDP Symposium Uncovers an Inconvenient Truth with a Shot of 3D

RahulD

Every April the leading edge of the leading edge of semiconductor industry meet at the Electronic Design Process (EDP) Symposium to address design problems that make design more difficult than it should be. This was my first visit and chance to rub shoulders with the industry's gurus and to discuss the arc and future of EDA tools and the EDA industry.
The nice thing about the EDP symposium (often referred…
- 16 Apr 2010
SoC and IP: Comprehensive SSD eval puts four drives to the test

archive

Geoff Gasior at The Tech Report has just published a long and very comprehensive side-by-side comparison of four SSDs from Corsair, Kingston, Plextor, and Western Digital. He’s pulled the covers off the drives to look at the guts (and he names names of the on-board controller chips in the process) and Gasior then tests each drive in turn to come up with some really interesting comparisons. If you’re interested in how…
- 15 Apr 2010
SoC and IP: Micron using ONFI 2.1 and SATA 3.0 to leapfrog Enterprise SSDs over HDD performance

archive

PCWorld reports that Micron will soon be rolling out Enterprise-class SSDs based on 34nm, ONFI 2.1, SLC (single-level cell) NAND Flash devices. These drives will employ the 6-Gbit/sec SATA 3.0 interface specification to create an I/O channel with enough bandwidth to support the faster Flash. Doing so makes the soon-to-be-introduced RealSSD P300 SSDs more than competitive with 10,000- and 15,000-rpm Enterprise-class HDDs…
- 15 Apr 2010
System, PCB, & Package Design : What's Good About Allegro PCB Editor Groups? Look to SPB16.3 and See!

Jerry GenPart

With the Allegro PCB Editor SPB16.3 release, you can now allow groups to have elements added or removed.

The construction and disbandment of groups is now supported in both the General and Placement application modes. Groups are easily created in the working canvas by first pre-selecting multiple elements followed by the selection of the "Add to Group" command located in the context sensitive right mouse button "Add to…
- 14 Apr 2010

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.