• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Blogs
  2. Community Forums
  3. Cadence Community
Cadence Community
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  • Site
  • Search
  • User
Find Other Members ►
Subscriptions
Get email delivery of the Cadence blog (individual posts).
  • Twitter
  • Facebook
  • LinkedIn
  • Google+

Community


Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

  • System, PCB, & Package Design : What's Good About Innovation at Cadence? – It’s Alive and Well and Increasing!

    Jerry GenPart
    Jerry GenPart

    I'm switching gears this week from my regular SPB technical product posts to focus on an annual Cadence event - Cadence Innovation Day.

    Today Cadence will honor the 2008 recipients of the Excellence in Innovation Awards. This year, 35 winners will be celebrated amongst their peers from all geographies and organizations - 13 of this year's recipients are from locations outside San Jose.

    Adam Sherer is one of this…

    • 3 Nov 2009
  • Analog/Custom Design: Things You Wish You'd Thought Of...But You're Glad Someone Did!

    stacyw
    stacyw

    On Tuesday this week we are celebrating "Innovation Day" here at Cadence, honoring inventive engineers across the company. 

    I must admit that most of the time I get so bogged down with the latest customer questions or figuring out how to help people learn about the latest features that I forget about all those folks in R&D whose raison d'etre is to come up with new and better ways of doing things.  And…

    • 3 Nov 2009
  • Verification: Emulation Is Here To Stay

    Ran Avinun
    Ran Avinun
    A recent blog by Brian Bailey covered the emulation war. I would like to correct some of the facts Brian has mentioned and also add my own comments. First, Brian, you owe Cadence an apology :)  You forgot some of the emulation announce...
    • 2 Nov 2009
  • Verification: From Cadence Earning Call This Week

    Ran Avinun
    Ran Avinun
    In system development, we have focused on two key customer challenges. First, we are increasing their productivity by elevating design and verification to the next level of abstraction. This quarter, we announced the industry’s first tr...
    • 2 Nov 2009
  • Verification: Improve Productivity Through Communication and Learning

    jasona
    jasona
    I regularly spend time talking to people about the importance of the connection between embedded software and hardware design and verification. If you have been following my writing on cadence.com you know that it takes more than tools to succeed on ...
    • 2 Nov 2009
  • Verification: OVM Tricks and Treats

    Team genIES
    Team genIES

    Your kids may be going house to house for treats, but you can get a big OVM sugar rush from Cadence's OVM World contributions.  Each delectible nugget is wrapped in documentation that helps you savor all the goodness. So reach into the bowl and indulge in these methodology sweets!

    Callback Mechanism

    From day 1 the OVM has employed a factory mechanism for both simple reuse and multi-language consistancy.  While factories…

    • 30 Oct 2009
  • Verification: Why Verification Engineers Are Like Football Players

    Adam Sherer
    Adam Sherer

    Is it their raw power?  Is it the cheerleaders?  Why are verification engineers like football players?  It's because they know how to squeeze the maximum performance out of their resources to win the verification game. Charlie Dawson, Senior Engineering Manager at Cadence, has been leading teams that build performance into our products for years and has taken some time to put the whole game in perspective.  Read more…

    • 30 Oct 2009
  • Digital Design: Encounter How-To: Write Text to The Log File With "Puts"

    BobD
    BobD

    Here's a simple but useful tip that shows how to write to the log file using the Encounter command "Puts"...

    In TCL, the "puts" command is use to write information to the console -or- to a file.  For example:

    encounter 63> puts "hi"
    hi

    -or-

    encounter 64> set outfile [open test "w"]
    file18
    encounter 65> puts $outfile "hi"
    encounter 66> close $outfile
    encounter…
    • 30 Oct 2009
  • System, PCB, & Package Design : What's Good About Net Color Override in Allegro? Check Out The SPB16.2 Release and See!

    Jerry GenPart
    Jerry GenPart

    Color assignment in Allegro PCB Editor has been accomplished with either a class/subclass color assignment or a color assignment done with the highlight command. With designs becoming more complex, it's desirable to be able to assign colors, including custom colors to independent objects.

    Database elements may be displayed using either the class/subclass color or a single color assigned to an element, also known…

    • 29 Oct 2009
  • Verification: 4 Minute Demo: OVM e Compliance Checks Added to AMIQ's DVT

    teamspecman
    teamspecman

    Specmaniacs rejoice: long time Verification Alliance partner AMIQ has just added OVM e compliance checking to their "DVT" integrated development environment (IDE). Here is a 4 minute video demo with the highlights of this new capability:

     

     


    If the fails to launch click here.

     

    To get the full scope of the DVT tool and AMIQ as a company, recall the 5 minute general demo of the tool in an earlier post,…

    • 28 Oct 2009
  • Verification: Where’s The “You” In The OVM?

    Adam Sherer
    Adam Sherer

    Cadence and Mentor have dedicated teams to the development and support of the OVM and you, our user community, have literally tens of thousands of developers dedicated to developing reusable VIP with it.  But where do “you” and the OVM meet?

    Sometimes the “you” is obvious – the OVM World Forum.  With 1100+ unique threads and 4500+ posts, the OVM Forum is by far the most active testbench and…

    • 27 Oct 2009
  • Verification: 4G Is Here Now

    Ran Avinun
    Ran Avinun
    If you have not heard about 4G yet, it is here now. Verizon has already paid earlier this year $9.4B for an open access to the new spectrum. It'll be using the spectrum as the core of their high-speed 4G LTE network - see below.http://g...
    • 27 Oct 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: ViVA

    stacyw
    stacyw

    Sorry I've been missing from this space for so long.  I've been busily working on a number of projects to try to help get the word out about all the features I have been (and will be) blogging about.  I've also been becoming an expert on making video demos, some of which I'll try to feature here too.  Ask your Cadence rep about the new VSE L/XL and ADE XL/GXL interactive Quick Start Guides.  (If they don't…

    • 27 Oct 2009
  • Verification: Keeping Trident Missiles "On Target" With System-Level Verification

    archive
    archive
    Can you think of a more critical application for system-level verification than making ABSOLUTELY CERTAIN a missile carrying nearly 5 Megatons of nuclear payload doesn't have any "bugs"? We've all seen enoug...
    • 23 Oct 2009
  • Digital Design: How To: Purge Interactive Constraints in MMMC Mode

    BobD
    BobD

    These tips are applicable to the Encounter Digital Implementation System.

    Back in the good old days, I remember asking designers at the beginning of a silicon virtual prototyping evaluation "Where is your timing constraints file?"  Note the singular form of the word file- was it really that simple?  Didn't seem so easy at the time.  While the complexity of timing constraints in terms of their content has increased…

    • 23 Oct 2009
  • Verification: Specman/IES-XL 9.2 Is Posted - Come And Get It!

    teamspecman
    teamspecman

    We interrupt the Specman 9.2 preview series and ClubT news to announce that 9.2 is now posted on downloads.cadence.com, under the "INCISIV92" umbrella!

    Hence, for those of you who couldn't get to a recent ClubT, CDNLive, or Incisive Seminar, our "9.2 preview series" is changing into the "9.2 highlights series", covering the major new features announced back at DAC.

    Happy Verifying!

    Team…

    • 22 Oct 2009
  • Verification: Why OVM? John Aynsley of Doulos Has 10 Reasons

    Adam Sherer
    Adam Sherer

    Believe it or not, sometimes a marketing guy just needs to say less. It's true. It does happen. Sometimes we do just get right to the point. Yeah, we do blather on sometimes but ... oops, there I go again. Just listen to John. He has 10 great reasons to adopt the OVM.


    If video fails to play please click here.


    Question? You can post them here or send them directly to John at john.aynsley@doulos.c…

    • 22 Oct 2009
  • System, PCB, & Package Design : What's Good About Package Power Integrity? You'll Need SPB16.2 To See!

    Jerry GenPart
    Jerry GenPart

    As clock and data frequencies increase and high-speed systems become ever more densely populated, the distribution of power becomes a major challenge for package power/ground design. To ensure that high-speed systems continue to deliver the required performance at these new signal frequencies, power distribution impedance has to be controlled over a wider range of frequencies. This can be accomplished through careful…

    • 21 Oct 2009
  • Verification: Demo: New Signal Tracing Capability in Incisive Enterprise Simulator

    archive
    archive

    One of the great things about working here at Cadence is having the opportunity to test and preview new features and functionality before public release.  The newly released 9.2 version of Incisive Enterprise Simulator contains a new streamlined signal tracing function in SimVision.

    I thought you might like to see a preview demonstrating the new capabilities for tracing signals directly within the source browser, as well as updates…

    • 21 Oct 2009
  • Verification: Extending Multiple When-Subtypes Simultaneously

    teamspecman
    teamspecman

    [For those of you that didn't / can't make it to a ClubT last week/this week, here is a meaty technical article from guest bloggers Matan Vax (R&D Architect), Yuri Tsoglin (R&D), and Dean D'Mello (CoreComp Architect)]

    When subtypes let you add properties and behavior to a struct or a unit when one or more enumerated/boolean fields take on specific values. The fields that define when subtypes…

    • 20 Oct 2009
  • Verification: Synopsys’ “Synphony” Announcement – Welcome to the Party!

    archive
    archive
    I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge produ...
    • 14 Oct 2009
  • Verification: Incisive Enterprise Verifier for Everyone!

    tomacadence
    tomacadence

    Last week Cadence announced a new product called Incisive Enterprise Verifier (IEV) that combines simulation and formal technologies in unique and interesting ways. I am very excited about IEV for two good reasons. The first is simply that it's the product I've been most involved with during my time at Cadence, so I have a personal stake in its success. The bigger reason is my vision that IEV will be the primary tool…

    • 14 Oct 2009
  • Verification: The Scoop on the New Incisive Enterprise Verifier

    Sarah Lynne
    Sarah Lynne

    Last week we announced Incisive Enterprise Verifier (IEV). What is cool about IEV is that it integrates formal analysis and simulation engines in unique ways that provide users with more power. One of the great things about IEV is that it is easy to use and get value quickly. It is all about helping to reduce the overall verification time.

    Take a look at the press release, and read Richard Goering's blog …

    • 13 Oct 2009
  • Verification: Webcast: EDA, ESL and More Ideas From DAC

    jasona
    jasona
    From the events calendar, OpenSystems Media is hosting a webcast tomorrow titled EDA, ESL, and More Ideas from DAC that will be hosted by Don Dingee and feature presentations and discussion from Frank Schirrmeister from Synopsys, Shabtay Matalon...
    • 13 Oct 2009
  • Verification: Virtualization and Simulation Roundtable

    jasona
    jasona
    A couple of weeks ago I participated in a roundtable discussion led by Peggy Aycinena that has been summarized and posted on edacafe.com. Please have a look if you are interested in Virtual Platform usage for embedded software.One of the things ...
    • 13 Oct 2009
<>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information