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Many of our customers use our Virtuoso software in combination with the windows emulation product from OpenText named "Exceed on Demand".   To maximize performance between the two tools, we have some recommendations: 

For IC6.1.4 and Exceed on Demand 7, these setting will cause problems between the two programs.  You should change the settings to the following:

Steve Lewis

This week, I'm taking a brief break from the usual PCB solution/product technical discussions and focusing on a very interesting capability used with the Cadence Allegro PCB Editor product.

You can read all the details from this article - Integrated Optical & Electronic Interconnect PCB Manufacturing in a recent PCB007 update.

 Most of you know that my primary focus is the "front end" environment for the Cadence…

[Team Specman welcomes back guest blogger, Michael Avery from our Services Group in the UK]

Building on the Part 1 introduction to Specman’s messaging built-in infrastructure, allow me to share some tips on how to programmatically control and scale message display to help shorten your debug time.

First and foremost: please, please, please avoid manually commenting out/in debug messages.  While it’s very tempting to…

Since I'm not a member of the Accellera VIP TSC, I did not attend the 2.5-day face-to-face meeting held last week in Massachusetts. But with the steady stream of tweets coming from several of those who did attend, I almost felt as if I were there. That experience will be subject of my next blog entry, but for today I want to touch on some of the interesting news from the face-to-face. Perhaps the most exciting was that…

[Team Specman welcomes guest blogger Michael Avery, from our Services Group in the UK]

Messaging is important for two main reasons:

• It is essential for debugging

• It can greatly impact simulation performance

This is why Specman has a messaging infrastructure built-in to provide an easy to use, scalable and efficient mechanism.  Furthermore, Specman’s messaging capabilities allow you to do almost anything which you can conceive…

You'll need to check into the nifty new probe capabilities in the SPB16.3 Allegro AMS Simulator release

These enhancements will improve your experience with analyzing simulation results especially for dense designs.

 These features include:

• Easy to use pop-up menu for traces
• Access to Trace Property and Hide and Show Traces
• Customizing auto-rotation of trace color from an enhanced color set
• Controlling background and foreground…

Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule.   A major stumbling block that can be a real threat to that predictability is iterations between different stages of the design flow. There are multiple reasons why this happens but one that should not happen is because…

I'm not going to beat around the bush here.  I could tell you about all the things that are new in ADE (Analog Design Environment) in IC 6.1.4.  I could tell you about the fact that the individual subwindows are now resizeable, rearrangeable (is that a word?), undockable and tabbable (I know that's not a word, but it's fun to say) just like the assistants in the main Virtuoso window.  I could tell you that the…

ARM-loving Specmaniacs's rejoice: we are now at liberty to announce that we are providing Verification IP (VIP) support for the new AMBA 4 protocol simultaneously with ARM’s introduction of said protocol.  Here is the official announcement, which includes AMBA4 and VIP highlights.

What this means in practical terms:

• If you have licenses for the Cadence VIP Portfolio (part number "VIP100"), you will receive…

Richard Goering's recent interview with Mitch Weaver on the future of Specman and e put me in a reflective mood about my own evolving opinions. My hands-on experience with Specman is minimal; back in my 0-In applications days I co-developed a joint demo with Verisity (prior to acquisition by Cadence) in which I had the chance to do a bit of e testbench coding. I was very familiar with formal at that point, but it…

Just a brief post this week to highlight one of the new SPB16.3 features in Allegro Design Entry CIS.

In complex designs containing a large number of parts, the task of wiring the parts together is often a time consuming and tedious task. Wiring multiple pins to a bus can also be a tedious and repetitive task. Capture now includes an Auto-Wiring feature that allows you to wire two or more pins or wires on your schematic…

Last week at DVCon, frequent Team Specman guest blogger Matan Vax of R&D gave a paper on "Where OOP Falls Short of Verification Needs".  In the following video, Matan elaborates on his paper, where it becomes clear that OOP languages like -- well, you know -- are at an inherent disadvantage vs. AOP approach (like in e) when it comes to the unique requirements of verification.

Click here if the embedded…

Boy, you must think we're a few sandwiches short of a picnic over here at Cadence.  

A couple of months ago we came out with this great new Virtuoso software release (IC 6.1.4).  So, despite my best efforts to get you to use the recently-opened files list or to create bookmarks, the first thing you did after starting virtuoso was open the Library Manager.  (Don't try to deny it, I know you did...). 

So there's the Library…

Click here or on the image below to go to the annotated photo blog of DVCon 2010 Day 3.

The images and notes include highlights from:

• A paper on "Where OOP Falls Short of Verification Needs" (And there is also a video interview of Matan elaborating on the paper

• The paper "Tweak Free Reuse With OVM"

• A paper on "Mixed Signal Verification of Dynamic Adaptive Power Management in Low Power SoCs"…

I've spent much of this week at the San Jose Doubletree Hotel for DVCon 2010, and I have to say that it was a really good show. This is arguably the most important conference of the year for verification. DAC is lots bigger of course, but DVCon is really focused and there's a core group of colleagues and customers that always make it a fun and simulating event. Although DVCon is still officially the "Design & Verification…

Click here or on the image below to go to the annotated photo blog of DVCon Day 2.

Photos & notes include highlights from:

•  Brett Lammers' paper on "Apples to Apples HVL Comparison Finally Arrives"

• Lunch panel on "OVM found the bugs, now how do we debug them faster"

• Cadence CEO Lip-Bu Tan's keynote on "Breaking Through The Efficiency Barrier"

• Industry Leaders panel on…

This past weekend, several new enhancements and features were added to Cadence Online Support. I would encourage all customers to take a quick tour of these productivity enhancements. Below I've included some screenshots and examples of a few of these new and improved areas of Cadence Online Support.

Most of the new features you'll notice as soon as you login.

Email Notification is back, including an added notification…

A couple weeks ago, there was a good thread in the Digital Implementation Forums about managing buffering on nets between IOs and registers.  The post touched on a number of interesting topics, but one of the fundamental building blocks I'd like to expand upon in this blog entry is the fundamental task of writing to and reading from a file: File I/O.

It may seem like second nature for folks who use TCL-based tools like…

Click here or on the image below to go to the photo blog of DVCon Day 1.

While I've added descriptive captions to the images, allow me to address the FAQ: "How was the traffic on show floor?".  My unscientific observation was that the floor was a little lighter than last year, but this was a result of the tutorials being better attended and/or they "held" their audiences for longer.…

If you were looking for more evidence that the transition from RTL to ESL is gaining momentum, today at "Day 0" of DVCon (a/k/a "SystemC Day") you would discover plenty of supporting data points.  Here is a brief video interview with my colleague Steve Svoboda on the day's events, how far we've come from the first wave of SystemC hype back in 2000, and what Cadence is doing in this space:

The OVM SystemVerilog Class Library has built-in automation for many service routines that classes need for printing, copying, comparing and so on. OVM allows you to specify the automation needed for each field and to use a built-in, mature and consistent implementation of these routines. For each field you must use OVM field registration macros as in the example below:

     ...

     rand bit [15:0]           addr;

     rand…

Yeah, I know I'm a marketing guy but I really like this stuff!  For sure, we are going tech-deep in our tutorials and papers, but we are also setting vision and direction for verification in our keynote presentation.  For all of the details, visit our DVCon events page.  Highlighted below are two of the items that I think will be of special interest.

Tutorial: OVM Advanced Topics

With UVM based on OVM, this is a must see…