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Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? Well, now there's an easy way to check for that with the checkFiller command:
    
    checkFiller -highlight true

   

To get rid of the highlights, do this:

    checkFiller -clearHighlight true

Another thing that is often found near the end of the design flow is missing power vias. You may have an IR-drop…

Does the union of verification automation and IT+source code management tools get you all misty eyed?  If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have you gushing tears of joy.  Specifically, this video shows IBM's Tivoli, Rational, and STG solutions married to Cadence's Incisive Enterprise Verification solutions.…

A few weeks before DAC, I started working on a blog post about the number of small EDA companies that remain in the functional verification space despite the tough economic times. My interest in completing the entry and publishing on this topic was increased by the number of small companies that I saw at DAC for the fifth, seventh, even tenth year in a row.

I used to observe that in 3-4 years most EDA startups were acquired…

Wait, don't run away!  In this case I really mean "Read The Fantastic Manual".  A recent comment by a reader prompted a spirited internal discussion here at Cadence regarding our Help system.  I suddenly realized it had been ages since I even looked at it.  Seriously, when was the last time you clicked on that "Help" menu at the top of your screen?

So I started doing some exploring and discovered that…

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their trade show strategy -- his message is reproduced in full below.  Please post your comments here for the benefit of whole the community, or contact XJTAG apart from this forum via http://www.xjtag.com/company/contact.php

------
August 24, 2009
Subject: RE: UPDATE: please comment on XJTAG booth strategy at DAC 2009

Hi Joe

You have asked for my commentary…

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!]

[Team Specman welcomes Reuven Naveh from Specman R&D to introduce “his” new feature.]

Abstract
In Specman 9.2 we are extending the syntax of constraint declaration in a struct to support a user defined name and a string message in case the constraint…

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls", a pair of sales models stationed in the booth of XJTAG, Ltd., a supplier of IEEE 1149.1 boundary scan development tools.  The surprisingly strong reactions to this classic trade show strategy prompted me survey our community about the propriety of the XJTAG Girls for a B2B show like DAC.  Since I'm not certain how persistent…

I'm taking a break this week from the technical type posts to say THANK YOU to the people who make blogging a success.

Of course, Blogging and Blogs are only successful if they are read and people post their thoughts and questions to continue a discussion. The PCB Design Community members - customers, Cadence, and industry folks - have been a terrific team in posting both in the Blog and Forums. Truly, it is the readers…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about it.  But talk is cheap.  Can you really optimize a package footprint and a chip I/O padring such that that package and PCB costs can be minimized?

What if using a straight forward flow you could take the devices to which your chip needs to interface and place them on a canvass with your chip and package.  And then what if you…

The Design Entry HDL (DEHDL) usability improvements are many and significant in the SPB16.2 release!

The DEHDL product moves even closer to other Windows based applications, such as Capture CIS, Adobe Reader and Microsoft Office applications, in terms of the general usability standards. These changes provide support for common Windows commands and operations making Design Entry HDL more user-friendly and easy to use.

The…

We've gotten some good feedback about posts in this forum relating to dbGet and dbSet (the database access mechanism inside SoC-Encounter). I've been collecting interesting dbGet/dbSet lines over the past several months that I think are very useful. Some of these may be something you've wanted to do as well, or maybe they will serve as a starting point for a different idea or even a longer script. I gave credit to the…

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions.  In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature stability.  As Chris mentions, the challenge of managing power paths is complicated by the need to carve up power planes into swiss cheese like structres around high pin…

Well, I had good intentions of blogging from DAC, or at least summarizing my four days there when I was back in the office on Friday (July 31). But I returned to a very busy week of actiivties that got bunched up together partly because so many Cadence people were at the show. At this point, I can offer a look back rather than a real-time update. More of a repeat than a tweet, given that many of my fellow bloggers have…

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso) article this week before I go on vacation, but you know how it is when you're trying to get out of the office for a week.  Things just seem to pile up higher than usual.

So in place of the usual witty repartee and pithy comments, I'll leave you with some pointers to some of the Virtuoso webinars that have been posted on Sourcelink…

As much as the Design Automation Conference (DAC) is about demonstrating solution capabilities to potential customers, it is also about personal connections.  Reconnecting with old and current colleagues, and making new connections with people in the design community you haven't had a chance to meet before is as important as anything else you might do at DAC.  Maybe it was just me, or maybe it was because of Twitte…

One non-technology item that received an extraordinary buzz at DAC 2009 were the XJTAG Girls:

For those of you not at DAC, these sales models were effective in persuading passers by to trade contact info for a chance to win a portable GPS or iPod.  Of the 5,135 combined exhibits-only and conference attendees, I'd conservatively guesstimate that the XJTAG Girls scanned about 7,500 badges.

As I can attest…

No - we're not talking teeth, candy, and cavities here ...

Many customers have been asking us to support cavities inside of the Cadence IC Packaging tools for a number of years now. These are most frequently requests from companies trying to design leadframe packages (a technology that Cadence does not support within either the APD or SiP toolsets), though some have come from customers wanting to embed a die within…