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I've told you in previous postings about some new features in Virtuoso IC6.1 which make it quick and easy to open cellviews you use frequently--namely the recently-opened files list (found in the CIW->File menu) and the ability to bookmark one or more cellviews (File->Bookmarks->Add Bookmark from any cellview window).

While these features mean that you can open that cell you work on every day with just a…

Specmaniacs,

With the start of DAC 2009, Team Specman is excited to finally be able to make public what we have in store for you in Specman/IES-XL version 9.2 this September.  Additionally, consider this post an open invitation to join the 9.2 beta program that officially starts next week on Monday August 3.

If you are at DAC, please seek out the Specmaniacs at DAC listed in our last post to learn more.  Otherwise, your local…

The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today.   Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one to debug when we scale the number of states, number of inputs, and consider asynchronous events.  While…

I'm looking forward to heading out to San Francisco next week for the 46th Design Automation Conference.  For my money, it's hard to beat San Francisco as a location for a trade show. Cable cars, Fisherman's Wharf, Alcatraz, San Francisco Giants baseball, Napa/Sonoma Wine Country...what a great part of the country.  And DAC itself is a great time in my experience.  You get to learn about all the latest things…

The following are the "must see" items for Specmaniacs lucky enough to get travel authorization for DAC 2009 (and/or who scored a cheap ticket on Priceline.com for a spur of the moment "vacation" to scenic San Francisco).

1 - Specman in the Cadence Main Booth (#3751, North Hall)
Given Specman's long support for ESL and TLM flows, Specman is featured in the TLM-driven Design&Verification suite…

In prior releases, Allegro PCB Editor does not provide the user the ability to place or make placement changes easily. New functionality to provide greater usability for component placement, alignment, replication of circuitry would greatly impact the time to get a design to fabrication.


The SPB16.2 Allegro PCB Editor introduces the 4th application mode; General, Etch Edit, IFP and now Placement available to Allegro PCB…

Yours truly will be at the big show next week, and I hope that all of you in the blogosphere will be able to sweet talk your management into letting you go as well. For those of you who have already won a golden ticket:

* By all means let's meet in person. When not in a customer or partner meeting, at various times I'll be on duty for Enterprise Verification at the main Cadence booth (#3751, North Hall), or supporting…

Some background info:
In a previous blog, I introduced:

• DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction.
• RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings. See “Part1: Using wreals to simulate Frequency Scaling for Dynamic Power Reduction” for details …

By now, you've probably seen that Cadence is participating quite heavily in DAC this year. Many of my fellow bloggers will be there, as will I. This will make DAC #22 for me, and I'm still looking forward to it...

(Parenthetical comment: I know that I'm dating myself in this post, but in the Internet Era anyone can easily search my name and see that I had my first IEEE publication way back in 1981. So can I indulge…

Recently our colleagues on Team ESL announced a new TLM-Driven Design and Verification Solution.  Team Specman guesstimates that about 15% of Specmaniacs are already using Specman with SystemC and/or some form of transaction-level modeling (TLM) flow.  For those of you that are in this camp, a logical question is "what's new"?  In advance of DAC (and the ClubT's this fall, and more detailed follow-up blog posts…

Hello,

As a member of the technical committee and as the chair member for the Analog and Mixed-Signal Design and Verification track, I would like to invite you to submit an abstract to this conference.

We solicit papers for two types of sessions: technical papers and tutorials. Technical papers, which are up to 25 pages long, address design case studies and application overviews, and are presented in forty-minute sessions…

"Tackling formal assumptions through verification planning" is a recent article by Chris Komar and Frank Armbruster that is available on EDN. This article has fun with the old adage about what happens when you assume but very quickly get serious and applies it to functional verification and specifically formal property checking. It talks about potential problems of assumption escape and walks thought how this can…

The OVM provides the most comprehensive reuse if you follow the methodology it prescribes. While its unique built-in classes are the technical heart of the reuse, you still have to write your own components. Now you have the new Paradigm Works OVC Template Generator to write them in the right way for you.

Paradigm Works, an industry leader in functional verification services has helped clients verify complex chips…

People say I have strong google-fu.   Whether it's finding information on a homework topic for my kids or reviews for that little restaurant downtown, all it takes is a minute or two at the keyboard and there it is.  Searching for information has become a very important skill in today's world, both in "real life" and at work.  Laying your hands on reliable information quickly can make your life easier, amaze your…

In the course of performing design work in Encounter, it frequently becomes desireable to create a self-contained testcase that can be shared with colleagues at other sites, or with Cadence to aid in troubleshooting tool issues.  By self-contained, I mean the design data (netlist, floorplan, placement, routing, timing constraint files, etc) and all of the supporting collateral (.libs, LEFs, extraction tech files, etc…

Another design approach that Cadence supports that may not be obvious to all users…

The process of setting up a circuit simulation has historically been one of setting up all of the simulation control parameters (i.e. which analysis you want...

First - ABIML is an acronym for Algorithm-Based Interconnect Model Library.

Currently, the model in the interconnect model library (IML) can only be reused by matching model name, model type, or exact "TraceGeometryData", which includes key information such as shield layer, dielectric layer, trace layer and the exact trace physical geometry. If any of the model geometry data is mismatched, the field solver is called to…