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[Please welcome Yuri Tsoglin of Specman R&D to the guest blogging rostrum.]

As my colleague Hilmar van der Kooij noted in a previous post, e's "defined as computed" macro capability is a great way to condense repetitive blocks of code into a few easy to read, parameterized lines. Building on Hilmar’s practical introduction, I’m going to ask you to take a step back and look at macros in broader context: specifically…

Some background info:
Taking a quick look at Power dissipation in CMOS:

Leakage power is well managed by powering down parts of the design when not in use. This is a well understood problem and can be simulated well in IUS (Incisive Unified Simulator) using CPF (Common Power Format) commands to capture power intent. For details refer to “A practical Guide to Low Power Design” – download a copy at …

Hello All,

Last week over in the LinkedIn Design Verification Professionals group, a thread came up in the discussion area regarding support for AOP in VERA.  The discussion quickly changed to the benefits of AOP for Verification.  Unfortunately, for the user who kicked off the thread, most of the other respondents seemed to only have experience with VERA's limited AOP capabilities and not with the more complete implementation…

Imagine this scenario: Your chip is a low power design. You’ve used everything in the book – clock gating, multiple threshold optimization, power shutoff, multiple supply voltages etc. What else can you do to reduce power in your design?

Or, maybe you can’t do power shutoff – the entire device is always on. Maybe you can’t use multiple supply voltages (face it – if you’re already running at 0.8V, how…

A few years ago I bought a wonderful book called "Earth From Above".  An amazing French photographer has put together a collection of truly unique aerial photographs of all kinds of unusual natural and man-made landscapes.  It's fascinating how different things look from high altitude--sometimes you can hardly recognize what you're looking at.  You wonder what that same scene would look like if you were…

Specmaniacs rejoice: there is a new blog centered around verification with e/Specman by Sandeep Gor:

http://digitalverification.blogspot.com/

Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are some other e/Specman-oriented sites we know of, and by all means please send us links to any sites that are missing from this list so we can promote them:

* The venerable Specman…

Earlier today at the Cadence San Jose campus, a charity event was held off-cycle from the regular "Stars & Strikes" charity event series, where this time the focus was on food with a hot dog eating contest to benefit for Second Harvest Food Bank’s "Share Your Lunch Drive".

For more images from the event, click here for an annotated gallery

This event might seem like it's coming…

For EDA software, it seems that it takes just as much effort to develop a methodology to use the software, as writing the tool itself. Ask any CAD group or design group that has to develop their own methodology and you can quickly gauge the many challenges in building a flow for your favorite EDA tool.

Why is it so hard to build and maintain a working flow? There are many reasons. First of all, EDA tools change.…

I read a recent article (June 11, 2009) in EDN magazine - "USB 3.0: A simple Idea Full of Challenges" by Ron Wilson.

In a nutshell, Ron says "Super-speed USB (Universal Serial Bus) 3.0 sounds like a great idea. Just start with widely used, fast, and bulletproof USB 2.0 and graft in the PHY (physical-layer) interface from another common and reliable standard, PCIe (peripheral-component-interconnect…

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer.  So much of my time was spent on design and verification, there was little time to explore all the capabilities of the software.

With that in mind, I'd like to share a demo of a new signal comparison utility, SimCompare.   You can do interactive comparisons…

Just a short post this week, as I've been quite busy recording videos for some of our Virtuoso Platform Webinar Series, the last of which, covering Spec-Driven Design, airs Tues. June 30.

Recordings of this and past webinars can be found here. (If not posted there yet, they will be available soon).  They've called these the 300-series webinars, a college course numbering analogy to let you know that you'll be getting…

In "Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic steady-state analysis was introduced. An example of using periodic steady-state analysis [PSS] to simulate the dynamic performance: THD and SFDR, of a switched...

Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI.

Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions to your simulation. Here is an example of a package I created to contain the math functions:

To allow for increased solvability, some constraints that were previously uni-directional with the old “Pgen” generator are now treated by IntelliGen in a bi-directional manner by default.  This behavior dramatically improves solvability and gives you a lot more freedom in writing and layering very complex constraints. 

However, if you are coding with a Pgen frame of mind there is one case where the results…

In order to complete a brand new design on time, it is an important factor to effectively reuse existing design modules. The use of an automatic optimization quickly and easily increases design reuse efficiency. The following figures are examples of a source layout and an optimized result made by Virtuoso Layout Migrate. Virtuoso Layout Migrate optimizes a design automatically by satisfying design specific constraints…

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009).  In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 --…