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In order to complete a brand new design on time, it is an important factor to effectively reuse existing design modules. The use of an automatic optimization quickly and easily increases design reuse efficiency. The following figures are examples of a source layout and an optimized result made by Virtuoso Layout Migrate. Virtuoso Layout Migrate optimizes a design automatically by satisfying design specific constraints…

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009).  In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 --…

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting the new FPGA System Planner (FSP) product from the Cadence Silicon Package Board (SPB) division at the recent CDNLive! EMEA event.

You can watch Hemant from the event:

Available in two forms - Allegro FPGA System Planner and OrCAD FPGA System Planner - this new technology…

I apologize for the Internet slang in the title (urbandictionary calls OMG "the most irritating piece of chatroom vernacular in existence"), but I couldn't resist.  Ever since IC6.1 came out, it seems like every other question gets answered using the three-letter acronym (that's TLA for those in the know), RMB.  RMB to open an assistant, RMB to do this, RMB to do that.  If you can't find it anywhere else…

On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions. A few of the published items do not accurately describe the actions that were taken, and we’d like to set the record straight. …

Team Specman is about to start a project to refresh the e/Specman Quick Reference card included with every Specman/IES release. (While the basics of the current card are OK, we concede some of its content is getting a little long in the tooth). Hence, please let us know your preferences about what we should edit, add, or subtract from the next version of the card in the comments below, or contact us directly offline.

For…

Starting June 23, 2009, Cadence technical experts will host a series of technical webinars on myriad of topics. During this free webinar series, you’ll discover possible solutions and best practices to overcome the challenges you may be facing today or ones you’ll soon be facing. Learn new applications and methodologies, ask questions, and follow up with our technical experts after the event to continue the…

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is buzzing this week about the OVM running on VCS. We first saw a post on the LinkedIn "OVM Professionals Network"on Monday June 15.  Today we saw a more detailed posting at IntelligentDV specifically stating a released version of VCS that will run the OVM.

For nearly two years we have talked to many VCS users who wanted to access…

Recently I had the honor of delivering the introductory section of a detailed demo on "Metric Driven Verification 101" given by my colleague Nick Heaton, an Architect in our Verification Solutions organization.

Specifically, after a few introductory slides by yours truly set the stage, in the video Nick shows in detail the methodology behind metric driven verification ("MDV"), and how it improves…

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development environment (IDE), AMIQ has seen a spike in interest in the tool (yeah!)  Given the particular interest being shown by Specmaniacs, AMIQ has forward us the the following tech tip about how you can point to Specman’s HTML docs, AND how you can search through the docs from inside DVT itself.  (Recall that DVT is…

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the FSP product in his Blog post - Innovative Approach to Optimized FPGA Pin Assignment


For an interesting interview about the new FPGA System Planner (FSP) product, please read the details here.

Here are some "take-aways" from Hemant's interview that I found noteworthy:

• Our customers are leveraging the power, design flexibility…

I keep my toothpaste in my bathroom.  I keep the paprika in the kitchen.  I keep the band-aids in the bathroom near the living room.  Two points here.  First, I keep the tools I need near the place where I do the activity for which I might need them.  Second, I try to always keep things in the same place so I know where they are when I need them.  Sounds sensible, right?  Dinner would never be ready on time if I had to keep…

There is a cool feature in the OVM library and Incisive Enterprise Simulator that comes to the rescue.  It is the built-in OVM transaction recording.

Modern metric driven testbenches generate a lot of dynamic data on the fly during a simulation…

Simulation is a huge topic.  Performance, debug, mixed-signal, low-power, assertions, coverage, IEEE languages, lint checking, interfaces, and much more.  Many of us started using simulation when it was gates and waveforms while others joined in the era of complex, multi-language, testbench-driven simulation. Regardless, the pace of design and verification is accellerating for all of us.  So how can we get those pearls of…

[Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share some important tips on the famous “vhdlsync” switch]

As users with mixed VHDL and Verilog environments know, even in this day & age mixed HDL simulation cycle semantics are not very well defined.  Even worse: there is no standard that specifies the order of execution of always blocks and VHDL processes, which can lead to simulation…

As noted in a prior post, I had the pleasure of attending a DVClub talk given by Brian Bailey entitled "Is it time to declare verification war?". As suggested by the word "war" title, Brian drew many analogies between the legendary text The Art of War by the Chinese general Sun Tzu, and the strategic and tactical challenges of verifying a complex device under test (DUT), complemented by introductions…

Yeah, right...in this economy, don't talk to me about real estate.  But I'm not talking about home prices, I'm talking about that territory on the screen right in front of you where you spend your day drawing and clicking and arranging and rearranging in order to accomplish your job.  Cadence has given you lots of tools to help you develop your little plot of land.  Just recently in this blog, I've told you about…

For those Specmaniacs using the REAL number data type & ports capabilities in Specman, you might be interested in a webinar our analog colleagues are hosting tomorrow (June 10) from 07:00- 8:15 AM (PDT) and a second broadcast at 10:00 -11:15 AM (PDT).  Specifically, the webinar is titled "How to Boost Performance for Mixed Signal SoC Top-level Verification", and it will address how to handle mixed signal design…

If you listened to Tom's advice on this blog two months ago and registered for the International Microwave Symposium or the RFIC symposium, then you should be at the Boston Convention center now enjoying RFIC talks. Please remember that we are waiting...

As noted in white papers, prior posts, and the Specman documentation, since IntelliGen is a totally new stimulus generator than the original "PGEN", there is usually some amount of effort needed to migrate an existing verification environment to fully leverage the power of IntelliGen.  To help expedite this process, I've just posted in the Community's Shared Code area a simple utility that allows you to…