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In this last segment of the series on performance-aware coding, allow me to share with you two tips on improving the performance of Temporals.

Temporals Performance Tip 1: Setup a "Synch Unit"
If you don't already use a synch unit - I recommend you setup one up now. Here's why: the synch unit contains ports connected to the device under test, and it defines events based on these ports. Thus, when working…

If you are an RFIC designer then I hope you are planning on attending the 2009 RFIC Symposium and the International Microwave Symposium (IMS) which will be held in Boston, Massachusetts, as the centerpieces of Microwave Week 2009, scheduled from Sunday...

If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is “a lot”.

If you have read my bio, I came to Cadence from Simplex and so power integrity analysis is close…

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was unthought of just 10 years ago: people working on laptops, accessing wireless internet at broadband speeds. I don't know about you, but to me, that is simply amazing. Imagine, 10 years ago we would have been content with surfing the internet at 56k dialup speeds. Now, we've come to expect consistently fast broadband speeds. If a website takes…

FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been absorbed into OVM, or what?

Answer 1:
The good news is that the "System Verification Methodology", or "SVM" for short, is alive and well. First, its documentation and examples have been always been part of the Cadence® Incisive® Plan-to-Closure Methodology since "IPCM" was released in December 2006. Fast forward to the…

I decided to switch gears a bit and write about an interesting article I read in Electronic Engineering Times (April 6, 2009) - "Social networking: Boomer adoption Up, Gen Y Flat" by Junko Yoshida. 

What I found fascinating is that us "old time" Baby Boomers are increasing the volume of blogs we read, social networking, and podcasts we listen to by 67%. Our counterpart Gen Y'ers (while having a larger…

It has been a while since I last appended, hope you are well!

It was a little bit difficult to come up with a subject to write about and then recently I was in a meeting where we were talking about transient noise analysis. A designer was discussing...

I found myself getting a little bit frustrated with some of the default colors that would come up in the VIVA waveform tool while I was plotting from the Analog Design Environment (ADE). After working with Kabir, the Product Engineer for VIVA, I discovered...

I suspect that in another year we’ll all stop talking about OpenAccess (OA) like it is something special and treat it the way it should be, that it is just another database. Having said that, I know I’m going to get plenty of email about my portrayal of OA from colleagues and others but that is the way I see it.

Let’s not fool ourselves, today OA is a big deal because it truly is a different way…

Allow me to digress from EDA subjects to herald the birth of my first child!

She arrived Saturday April 18 at 5:07am, weighing in at healthy 7 lbs., 1 oz.

Mom and baby are doing fine.

As you may expect, I'll be taking a break from blogging for a few weeks, but of course Team Specman and the whole Functional Verification and Systems Design & Verification blog streams will continue to inform & enlighten…

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve the performance of stimulus creation.  With this API you can create stimulus items in an efficient manner, and reduce the number of context switches between the sequence and its driver. For example, instead of many generation actions, you can simply send items from a list:

for each in input_list {
    driver.wait_for_grant(me);
    driver…

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent anything other than ... more stuff).

We're back to exploring the new SPB16.2 features in Allegro System Architect (ASA)/System Connectivity Manager (SCM).

TCL
For those who may not know - "Tcl (Tool Command Language) is a very powerful but easy to learn dynamic programming language, suitable for a very wide range of uses…

In this introductory Part I of V of this blog I will discuss the advanced node design challenges impacting CIC design convergence and the solutions to achieve expedited physical implementation convergence.

As designers move to 65nm technologies and below, the convergence of performance-driven design constraints and yield-driven manufacturing constraints intensifies the demand for new approaches for integrated circuit (IC)…

In my last post I shared how my annual tour of the tour of the ESC show floor inspired me to ask the community their preferences on trade show formats.  Since I'm not certain how persistent these free survey sites are, allow me to replicate a snapshot of the survey results from the official results page below:

Question: Which type of event do you prefer in general?
Booth-centric events (like ESC or DAC) --  44%, 8 res…

In my previous blog on noise analysis accuracy, I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise analysis expert Trisha Kristof, who’s been working on our SI analysis since the CadMOS CeltIC days, to guest blog on this topic.

A note from Trisha Kristof on…

IC designers and foundries typically have different objectives. IC designers want to achieve the greatest performance while performing the least amount of guard-banding. Schedules and predictability are also paramount concerns for designers. IC Foundries want designs to adhere to design for manufacturing (DFM) and design for yield (DFY) rules and recommendations for their advanced process nodes to achieve the highest…

The constraint solver is a powerful and fun to use tool.  Actually, it is so much fun that  sometimes people tend to use it in cases where generation is not required.  Of course, like any other algorithmic engine, the “price” of using the constraint solver is paid in performance – both memory and CPU.  This price is acceptable whenever the solver is used to process complicated generation problems, but it…

This is the last in the series of Constraint Construction blogs! Today we're going to go over DESIGN RULES and MODES OF OPERATION.

DESIGN RULES: Follow them, or else...

Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce noise issues. Or maybe you want to give yourself some margin of safety with minimum capacitance. Let's go over the…

That's right - the SPB16.2 release now includes support for Physical and Spacing (P&S) Constraints from within the Design Entry HDL Constraint Manager.

Prior to this release, you could only set electrical constraints in Design Entry HDL Constraint Manager (CM). Beginning with the SPB16.2 release, in addition to electrical constraints, you can use Constraint Manager connected to Design Entry HDL to create, view…