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I'll be live blogging from the Cadence Campus in San Jose today.  We're doing a seminar that focuses on the 8.1 release of the Encounter Digital Implementation System, and we'll be focusing on the following areas:

• Design Closure
• Mixed Signal
• Low Power
• Advanced Node
• Analysis & Signoff

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware e coding to point out a new blog we just discovered on "e verification" by Shivayogi, "a Senior Design Engineer, working in the field of verification for more than 5+ yrs".

http://e-verification.blogspot.com/


Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are…

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC), with the added bonus of catching the panel discussion on "Who's Taking Over Whom - Is EDA moving Into Embedded or Embedded into EDA" supported by Mac (a/k/a Michael McNamara). While this panel was very engaging, (check out fellow blogger Steve Brown's account here), instead of blogging about the panel I've been inspired to step…

Building on Part 1 where I talked about the “do’s and don’ts” of List performance, in this segment on performance-aware coding I’ll show you some memory saving tips.  We base this segment on base types (geeky pun intended) …

Base types extensions
Creating base classes with functionality that is common to many environments is a good practice.  In this way you “develop once” (and even more…

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark Knight?  Well, thanks for indulging me, I hope the suspense wasn’t too much to bear! As I mentioned in part 1, if you had taken the January 2009 SAT test, again, like my daughter did, you had this as one of your essay prompts:

Prompt 1
Think carefully about the issue presented in the following excerpt and the assignment below:…

In the late 70's and early 80's system level PCB and Digital IC physical design evolved from manual Rubylith and Digitizing methods. If I haven't dated myself already with the terms Rubylith and Digitizing I know that I'll really be dating myself with my history at IBM.  While working for IBM in the General Products Division San Jose, CA during this period of time I used an IBM proprietary EDA application…

This past week, there has been a very interesting discussion on the "icu-pcb-forum" Email alias. Most of the people have migrated to our Cadence Support forums, but there are still a few that use the "icu-pcb-forum" Email alias.

The topic - Schematic drafting practices.

There are some "veteran" designers (several with more than 25 years of experience) posting their perspective and company practices…

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5 part series on performance-aware e coding guidelines.]

As all Specmaniacs know, the "e" language is flexible and powerful, containing many constructs that allow users to implement virtually anything. The downside of this freedom is that sometimes developers do not make the best choices when it comes to writing efficient code…

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering to the team. Anyone who has been involved in EDA in the past 20 years surely knows and respects Richard.

Personally, I spent about 10 of those years in Design, Verification, and CAD management, where I always read Richard's articles and columns for their keen insight into the tools I used or should consider using. The last 10…

At a purely technical level, Process Design Kits are fairly innocuous. They are used to enable custom IC design flows. A Process Design Kit (PDK) includes device models, schematic symbols, netlisting procedures and parameterizable cell layout generators. Physical verification rule decks and a parasitic extraction technology file are usually included in the kit. Quite a few of the tools used in custom IC, such as placers…

Every analog circuit design goes through some kind of electrical validation step before release to manufacture. The depth and breadth of this testing depend on the design itself, the end application and of course that all important deadline. When it comes to custom design, there is also an individual factor, as different engineers have different ideas on what validation is required. For example, on one end of the spectrum…

[Please welcome Markus Winterholer to the Team ESL blog.  Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.]

At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title "Metric Driven Functional Verification of Embedded Software" which caused a lively discussion started by Assistant Professor Dr. Winfried Dulz from the University of Erlangen…

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight.

Well, first of all, it has only been in the past few years (so this, obviously isn’t something I’ve had to do!), but today's high school students now have to answer essay questions on the SAT test, in addition to the traditional verbal and math sections. This is to test their writing skills in preparation for college. Writing skills…

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were:

• Security (the focus of Part 2 of this series)
• EDA applications that can clearly benefit from SaaS
• Bandwidth needs
• Configuration control
• Dealing with and/or migrating legacy flows & data

Having addressed the security issue in my last post and/or putting security aside…

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen & Krishna, having "perfect correlation" for timing from RTL to Signoff can dramatically improve design closure and cycle time which…

Last night when I was waiting for my daughter to finish orchestra rehearsal (she is a violin player in the Greater Twin Cities Youth Symphony) I was reading an article in the latest issue of Communications of the ACM with the title "Is Software Engineering Engineering?".  The article covered topics are near and dear to me both as an engineer working in a company that produces software and as a producer of software…