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Latest Blog Posts

  • Verification: Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

    archive
    archive
    Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009.   With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attend...
    • 3 Oct 2009
  • System, PCB, & Package Design : What's Good About APD's Design Integrity Check? - It's in SPB16.2!

    Jerry GenPart
    Jerry GenPart

    The Cadence IC Packaging tools are complex, flexible tools that allow a designer freedom to create a package substrate layout in a myriad of ways. As a result, it becomes possible to run a particular feature at a time when the database is ill-configured to handle the request. Or, a given command could have a bug which results in the corruption of a specific database object in a manner that is not illegal to the database…

    • 30 Sep 2009
  • Verification: The Power of Parallel Thinking: Multi-Core Cadence

    tomacadence
    tomacadence

    A while back, as we were preparing to launch our first phase of multi-core support in the Cadence Incisive Enterprise Simulator family, we started working on a press release. We decided to include the multi-core support added recently to Incisive Formal Verifier, in which formal engines can run in parallel to deliver assertion results faster. Then Yoon Kim, my neighbor in the next office, mentioned that Conformal Equivalence…

    • 30 Sep 2009
  • Verification: Using Vera is like Speaking Sumerian – Who’s Left to Understand?

    Adam Sherer
    Adam Sherer

    Just like natural languages, non-standard verification languages can fade away.  Sure, ancient Sumerian exists in the Code of Hammurabi, but all modern law is written in living languages.  Similarly, verification environments and VIP still exist in Vera, but a shrinking population understands and uses it.  To preserve the investment, that code base need to be both translated into a standard language like SystemVerilog…

    • 30 Sep 2009
  • Verification: Verification is a Sprint and a Marathon!

    Adam Sherer
    Adam Sherer

    Verification engineers have updated an old adage to discribe their projects:  Verification is both a sprint and a marathon!  We need to optimize everything from single simulation runs to the complete suite of regression tests and every task in between.  Cadence answered that comprehensive call in the Performance Leadership announcement issued September 29th, 2009.

    This intrepid blogger thrives in the land of performance and…

    • 30 Sep 2009
  • Verification: CDNLive San Jose 2009 for the Specmaniac

    teamspecman
    teamspecman

    Even sooner than the EU ClubTs is CDNLive San Jose 2009, where this year the event is a "hybrid" format of in-person workshops and on-line webinars.  As with past CDNLive's, the agenda spans the entire Cadence product line, subdivided into tracks for the major segments of the design & verification flow.  Of course, Functional Verification and System Design & Verification are major tracks:

    http://www…

    • 30 Sep 2009
  • Verification: EU Specmaniacs: ClubTs Are Coming in 2 Weeks!

    teamspecman
    teamspecman

    EU-based Specmaniacs and "Trailblazers" rejoice: the annual ClubT series is back!  As always, these free events feature direct contact with Cadence R&D and Methodology experts to share developments in advanced verification, updates to the "Trailblazer" program, and hear your emerging challenges and concerns.

    In fact, we welcome YOU to present at ClubT!  If you have a 30-40 minute presentation on verification…

    • 29 Sep 2009
  • Verification: Must Have Advanced Verification to Achieve Software Signoff

    Steve Brown
    Steve Brown
    In a recent blog on EDA Graffiti,  Paul McClellan he talks about Software Signoff. He loosely defines it as high level synthesis of C/C++ describing the system, with some of the code built into an FPGA and the rest remains application software. ...
    • 24 Sep 2009
  • Verification: Specman 9.2 Preview: A Fresh Profile on the Profiler

    teamspecman
    teamspecman

    [Preface: all features in the 9.2 preview series are in Beta now.  We invite you to sign-up for the beta program and give this feature a test drive!]
    [Team Specman welcomes Avi Bloch from Specman R&D to introduce one of “his” new features.]

    Abstract
    Starting in Specman/IES-XL 9.2, users will be able to split the profiling process into separate run and analysis phases. This allows users to generate a profiler…

    • 23 Sep 2009
  • Verification: Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

    jvh3
    jvh3

    I'm not proud to admit that I reacted with envy to the news that Twitter just received a $1 billion valuation.  This story inspired further chatter claiming that if Twitter plays their cards right, they could achieve a $5 billion valuation before long.  That's right: this fresh new internet combination of CB Radio, bad-but-fun TV, and primary source news, which barely existed even 1 year ago, could soon be worth more…

    • 23 Sep 2009
  • System, PCB, & Package Design : What's Good About Allegro's Component Placement Changes? - More Features in SPB16.2!

    Jerry GenPart
    Jerry GenPart

    In the SPB16.2 release of Allegro PCB Editor, there are two (2) new very helpful features (among the many others) that assist PCB designers with component placement - Component Alignment and Placement Replication.

    Component Alignment

    • You can now specify a Vertical or Horizontal alignment of symbols based on their body center.
      • There are no associated options.
    • The feature automatically attempts to determine the axis to align…
    • 23 Sep 2009
  • Verification: What's the New CMO Mean For Cadence and System Design and Verification?

    Steve Brown
    Steve Brown
    If you track Cadence stock or other EDA leadership news you undoubtedly know we've hired John Bruggeman as our new Chief Marketing Officer (CMO) and Vice President of Marketing. He's been part of some very dynamic companies, and most recently...
    • 22 Sep 2009
  • Verification: Upcoming ARM Techcon3 or is it Techcon Cubed?

    jasona
    jasona
    The annual ARM Developers' Conference has been renamed ARM techcon3, or maybe it is ARM techcon cubed. It will be held October 21-23 at the Santa Clara Convention Center. I'm hoping to get to the keynote by Cypress Semiconductor President and...
    • 17 Sep 2009
  • Verification: Specman-Matlab Package Update

    teamspecman
    teamspecman

    [Preface: we interrupt the Specman 9.2 Preview series to notify you of an update to the popular Specman-Matlab shareware package. Long before the term "crowd sourcing" was invented, our Application Engineers created and continue to maintain the venerable Specman+Matlab package described in this article. Guest blogger and Field colleague Jangook Lee is the latest to have refreshed it for a customer in Asia to support…

    • 16 Sep 2009
  • Verification: Back to School and Back to the Embedded Software Challenge

    jasona
    jasona
    The kids have a week of school in the rear view mirror and it's time to get back to the embedded software challenge.Remember when every EDA vendor started saying "Verification is taking 70% of the time on every chip design pro...
    • 14 Sep 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso ADE

    stacyw
    stacyw

    After delving into lots of new features in the Virtuoso Schematic Editor, the Library Manager and the Help System, I'd like to turn to our old friend ADE (aka Analog Design Environment, or for those of us who've been around awhile, Analog Artist).  ADE is another one of those tools that you're probably using exactly the same way you've always used it because--well, because that's the way you've always used it.…

    • 10 Sep 2009
  • System, PCB, & Package Design : What's Good About Eye Masks in PCB SI? You'll Need SPB16.2 to See!

    Jerry GenPart
    Jerry GenPart

    Eye masks let you specify the acceptable parameters for what an eye should look like in order to extract clock transmissions and high-speed data to buffer models. The current method of creating and saving eye masks is tedious. SigWave  has been enhanced to allow you to create eye masks that you can save in .sim files and view/edit when you display the waveform in Eye Diagram mode.

    One current use model for creating eye…

    • 9 Sep 2009
  • Verification: Incisive Enterprise Simulator: Low-Power Verification at Warp Speed

    Team genIES
    Team genIES

    Since your circuit always runs at low-power, your verification should too.  To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively.  In some cases that can result in tests that run faster with power analysis on than with power analysis off - engage the warp engine!

    IES introduced the most comprehensive native-compiled, low-power…

    • 9 Sep 2009
  • Verification: Requirements for a Student Version of Specman/IES-XL?

    jvh3
    jvh3

    Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by the back-to-school season:

    You may recall a question was posted to Mike Stellfox back in February about the availability of a limited, student version of Specman and IES-XL for the student's personal computer (vs. the full Specman/IES-XLs our University program partners are licensed to run on official school machines).  Unfortunately, Cadence…

    • 8 Sep 2009
  • System, PCB, & Package Design : What's Good About Split Parts in AMS Simulator? More Features in SPB16.2!

    Jerry GenPart
    Jerry GenPart

    This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. The PSpice engine can identify different sections of a split part and simulate them as a single component by intelligently combining the sections into one single part. At present, the Split Part support is available only in the AMS-DEHDL flow.


    Details

    The Split Part feature has been provided to allow users…

    • 3 Sep 2009
  • Verification: Specman 9.2 Preview: Shortened “When Subtype” Declarations

    teamspecman
    teamspecman

    [Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!]

    [Team Specman welcomes back Yuri Tsoglin from Specman R&D to introduce one of “his” new features.]

    Abstract
    The current syntax of "when" struct member declaration explicitly includes the base (parent) struct name, in the context of which it is…

    • 2 Sep 2009
  • Digital Design: Lost and Found: Missing Filler Cells, Power Vias, and Highlighted Objects

    Kari
    Kari

    Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? Well, now there's an easy way to check for that with the checkFiller command:
        
        checkFiller -highlight true

       

    To get rid of the highlights, do this:

        checkFiller -clearHighlight true

    Another thing that is often found near the end of the design flow is missing power vias. You may have an IR-drop…

    • 28 Aug 2009
  • Verification: Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

    jvh3
    jvh3

    Does the union of verification automation and IT+source code management tools get you all misty eyed?  If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have you gushing tears of joy.  Specifically, this video shows IBM's Tivoli, Rational, and STG solutions married to Cadence's Incisive Enterprise Verification solutions.…

    • 27 Aug 2009
  • Verification: Functional Verification and EDA "Startups"

    tomacadence
    tomacadence

    A few weeks before DAC, I started working on a blog post about the number of small EDA companies that remain in the functional verification space despite the tough economic times. My interest in completing the entry and publishing on this topic was increased by the number of small companies that I saw at DAC for the fifth, seventh, even tenth year in a row.

    I used to observe that in 3-4 years most EDA startups were acquired…

    • 25 Aug 2009
  • Analog/Custom Design: Things You Didn't Know About Virtuoso: RTFM

    stacyw
    stacyw

    Wait, don't run away!  In this case I really mean "Read The Fantastic Manual".  A recent comment by a reader prompted a spirited internal discussion here at Cadence regarding our Help system.  I suddenly realized it had been ages since I even looked at it.  Seriously, when was the last time you clicked on that "Help" menu at the top of your screen?

    So I started doing some exploring and discovered that…

    • 25 Aug 2009
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