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I found myself getting a little bit frustrated with some of the default colors that would come up in the VIVA waveform tool while I was plotting from the Analog Design Environment (ADE). After working with Kabir, the Product Engineer for VIVA, I discovered...

I suspect that in another year we’ll all stop talking about OpenAccess (OA) like it is something special and treat it the way it should be, that it is just another database. Having said that, I know I’m going to get plenty of email about my portrayal of OA from colleagues and others but that is the way I see it.

Let’s not fool ourselves, today OA is a big deal because it truly is a different way…

Allow me to digress from EDA subjects to herald the birth of my first child!

She arrived Saturday April 18 at 5:07am, weighing in at healthy 7 lbs., 1 oz.

Mom and baby are doing fine.

As you may expect, I'll be taking a break from blogging for a few weeks, but of course Team Specman and the whole Functional Verification and Systems Design & Verification blog streams will continue to inform & enlighten…

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve the performance of stimulus creation.  With this API you can create stimulus items in an efficient manner, and reduce the number of context switches between the sequence and its driver. For example, instead of many generation actions, you can simply send items from a list:

for each in input_list {
    driver.wait_for_grant(me);
    driver…

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent anything other than ... more stuff).

We're back to exploring the new SPB16.2 features in Allegro System Architect (ASA)/System Connectivity Manager (SCM).

TCL
For those who may not know - "Tcl (Tool Command Language) is a very powerful but easy to learn dynamic programming language, suitable for a very wide range of uses…

In this introductory Part I of V of this blog I will discuss the advanced node design challenges impacting CIC design convergence and the solutions to achieve expedited physical implementation convergence.

As designers move to 65nm technologies and below, the convergence of performance-driven design constraints and yield-driven manufacturing constraints intensifies the demand for new approaches for integrated circuit (IC)…

In my last post I shared how my annual tour of the tour of the ESC show floor inspired me to ask the community their preferences on trade show formats.  Since I'm not certain how persistent these free survey sites are, allow me to replicate a snapshot of the survey results from the official results page below:

Question: Which type of event do you prefer in general?
Booth-centric events (like ESC or DAC) --  44%, 8 res…

In my previous blog on noise analysis accuracy, I mentioned something called “double-clocking” and a few of you since then have asked for more information on what it is... So as a follow-up to that bog, I’ve invited our resident noise analysis expert Trisha Kristof, who’s been working on our SI analysis since the CadMOS CeltIC days, to guest blog on this topic.

A note from Trisha Kristof on…

IC designers and foundries typically have different objectives. IC designers want to achieve the greatest performance while performing the least amount of guard-banding. Schedules and predictability are also paramount concerns for designers. IC Foundries want designs to adhere to design for manufacturing (DFM) and design for yield (DFY) rules and recommendations for their advanced process nodes to achieve the highest…

The constraint solver is a powerful and fun to use tool.  Actually, it is so much fun that  sometimes people tend to use it in cases where generation is not required.  Of course, like any other algorithmic engine, the “price” of using the constraint solver is paid in performance – both memory and CPU.  This price is acceptable whenever the solver is used to process complicated generation problems, but it…

This is the last in the series of Constraint Construction blogs! Today we're going to go over DESIGN RULES and MODES OF OPERATION.

DESIGN RULES: Follow them, or else...

Often times, these rules are indeed set in the timing library. But perhaps you want sharper transitions in your design to reduce noise issues. Or maybe you want to give yourself some margin of safety with minimum capacitance. Let's go over the…

That's right - the SPB16.2 release now includes support for Physical and Spacing (P&S) Constraints from within the Design Entry HDL Constraint Manager.

Prior to this release, you could only set electrical constraints in Design Entry HDL Constraint Manager (CM). Beginning with the SPB16.2 release, in addition to electrical constraints, you can use Constraint Manager connected to Design Entry HDL to create, view…

I'll be live blogging from the Cadence Campus in San Jose today.  We're doing a seminar that focuses on the 8.1 release of the Encounter Digital Implementation System, and we'll be focusing on the following areas:

• Design Closure
• Mixed Signal
• Low Power
• Advanced Node
• Analysis & Signoff

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware e coding to point out a new blog we just discovered on "e verification" by Shivayogi, "a Senior Design Engineer, working in the field of verification for more than 5+ yrs".

http://e-verification.blogspot.com/


Team Specman, and we dare say Specmaniacs everywhere, welcome this new resource to the community!

Here are…

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC), with the added bonus of catching the panel discussion on "Who's Taking Over Whom - Is EDA moving Into Embedded or Embedded into EDA" supported by Mac (a/k/a Michael McNamara). While this panel was very engaging, (check out fellow blogger Steve Brown's account here), instead of blogging about the panel I've been inspired to step…

Building on Part 1 where I talked about the “do’s and don’ts” of List performance, in this segment on performance-aware coding I’ll show you some memory saving tips.  We base this segment on base types (geeky pun intended) …

Base types extensions
Creating base classes with functionality that is common to many environments is a good practice.  In this way you “develop once” (and even more…

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark Knight?  Well, thanks for indulging me, I hope the suspense wasn’t too much to bear! As I mentioned in part 1, if you had taken the January 2009 SAT test, again, like my daughter did, you had this as one of your essay prompts:

Prompt 1
Think carefully about the issue presented in the following excerpt and the assignment below:…