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Has something like the following ever happened to you?

You've placed and optimized a design, and you see what appears to be timing violations that could be fixed with cell changes on the worst path in the design.  Like the path below that has a lot of "X1" strength cells (don't worry, I contrived this case by timing the design prior to running optDesign to exaggerate the point):

If you wanted to…

I mentioned in my last post that I'd been having lots of fun with power switches lately. One thing I learned how to do was to set up a regular pattern for my switch columns. My first stop for learning something new is always the documentation, but there are so many different options to the addPowerSwitch command that I asked one of our experts, Richard Chou, for help. Setting up a pattern is really quite easy!

Here…

[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field Organization]

There is one very easy step that Specman users can take to roughly double the wall clock, run time performance of their testbench.  In a word, "compile"!

That's right: by simply compiling their e testbench, we've seen customers enjoy substantial performance increases, often up to 2x faster than uncompiled runs…

There's an interesting thread on Cool Verification (http://www.coolverification.com/2009/02/dvcon-misfits-unite.html) about the number of papers at DVCon 2009 authored or co-authored by EDA vendors. There seems to be an assumption on the part of some posters that vendor involvement implies marketing presentations. Not necessarily so! I've certainly seen some conference presentations that were nothing more than recycled…

If you were not lucky enough to be atDesignCon this week, and many of us were not!  You might be interested in the streaming interviews posted on line.  Click here for link.

Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's advanced node IC's.

Enjoy!!

And the new features list just keeps going on and on - it's terrific!

In the SPB16.2 release, the Allegro System Architect (ASA), and System Connectivity Manager (SCM) products have been enhanced to provide Differential Pair Swapping capabilities that interface with the Allegro PCB Editor product.

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1 and Part 2 of the series to get up to speed.

Today's topic is debugging. One of the great things about a Virtual Platform is the ease of debugging code running on the platform. In the first 2 segments we demonstrated how to compile the Linux kernel and run it on the ARM Integrator platform. As…

There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager for Virtuoso APS that elaborates on parallelization technology and how it's been used to deliver improved performance in Virtuoso APS. Take a look, click here!

This week the "DesignCon" show is in town (<= 10 minutes from the Cadence campus at the Santa Clara convention center), so I couldn't resist the opportunity to check out some of the speeches and exhibits.  I'm happy to report that my curiosity was rewarded -- here are my notes along with some photos:

* First, full disclosure: Cadence -- both Corporate and Chip Estimate -- have modest 10x10 booths on…

Allow me to direct your attention to a most welcome article in EDA DesignLine written by Gabe Moretti:

Title: [End] EDA bashing
http://www.edadesignline.com/213000305?cid=RSSfeed_EDAdesignline_edadlALL

In a nutshell, the article argues that general, blanket criticism of the EDA industry -- "EDA bashing" -- is unhelpful to say the least.  I couldn't agree more, and I assure you that my concurrence is not motivated…

Team Specman has been doing a great job supplying nifty tech tips and other useful information about using Specman. Recently, they sent us R&D types a request for new topics to cover. I quickly took them up on it and supplied a post about how to interactively debug when using the Specman Co-Verification Link. Joe asked if I would follow up to clarify the differences between CVL and ISX. These two things are slightly…

[Join Team Specman in welcoming guest blogger Jason Andrews.  Jason is a recognized hardware-software co-verification expert (he's written books on the subject!) and a fellow blogger]

One of the long-time features of Specman is "CVL". It stands for "Co-Verification Link", but is somewhat misnamed. CVL connects a host compiled C program to Specman via a network socket. This feature enables e methods…

I wanted to share some experiences I had with SpectreRF-Turbo and Parasitic reduction on a recent large benchmark. The things I learned may be helpful to anyone who wants to get the most out of turbo and parasitic reduction.

Available in MMSIM7.0.1 and...

One of the new features I mentioned in my previous entry on 3 Reasons You'll Want to Download Encounter 8.1 is the Foundation Flow. Have a look at this screencast for a demonstration of how to take an existing design loaded in the system and quickly get up and running with the Foundation Flow:

If the video fails to embed, please try here.

The steps described in the video are:

1. Load a design into Encounter
2. Select…

I've been having a lot of fun with power switch cells lately. That's a whole other story (and perhaps a future blog entry), but in my experiments I was able to use dbGet in some neat ways. I posted previously about getting started with dbGet here.

After you've experimented with dbGet for a while, the natural next step is to start using it in scripts or pieces of code.

The scenario: All of my switch cells were…

Cadence will present SpectreRF Noise aware PLL flow latest enhancements at the DesignCon 2009 conference, based in Santa Clara . In the paper "Noise and Jitter Analysis for PLL-Based Frequency Synthesizer", we fully describe SpectreRF flow and provide...

It's here! It's really here!!!

I've spoken with many customers over the past several years and so many have requested an automatic Table of Contents (TOC) generator for Allegro Design Entry HDL (DEHDL).

In most of the designs you construct, the first sheet (or sheets) of the schematic design contain a table of contents (TOC). The SPB16.2 release contains the functionality for creating and automatically updating…

While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:

Error! integer overflow

File: ./test.vhd, line = 13, pos = 11

Scope: :$PROCESS_000

Time: 10 FS + 0

./test.vhd:13 i := i - 1;

Incisive is probably the only simulator to report such error condition. The only other popular VHDL simulator was not able to catch/report this condition, when…

Specmaniacs and Other Trailblazers,

The latest edition of the 'ClubT' newsletter is now posted here, and once again there is exciting news around e, Specman, and Verification.  Articles include:

* Have you heard of OVM e?

* Incisive 8.2 Technology Update

* Verification IP Portfolio E-x-p-a-n-s-i-o-n

Note: We did not send a newsletter out last October since we ran the 'ClubT' events then (with over 200 total attendees…