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Latest Blog Posts

  • Digital Design: Turning the Downturn Upside Down

    Chi Ping Hsu
    Chi Ping Hsu
    Many bemoan the gloom and doom of the present economic situation, and it is true that some have been really hurt by it. Much is being discussed about the current downturn and its effect on virtually every industry. At the same time, there is also discussion of the 'upside of a downturn', where companies are energized to focus and innovate at even higher levels to help drive the recovery and prepare for better times. Many…
    • 20 Feb 2009
  • Verification: Tech Tip: Viewing The Combined Help for IES-XL

    adua
    adua

    IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode.

    One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very simple to achieve !!! So, I thought of sharing it here.

    Viewing the combined help for IES-XL product: As long as…

    • 20 Feb 2009
  • Verification: Tips for Opening Cadence Help

    teamspecman
    teamspecman

    [Welecome back the Tech Pubs team as guest bloggers]

    Sometimes you just need a little help -- fast.  Like right now; or even yesterday.  Here is the UNIX command to get you the online help you need for Specman and Incisive Enterprise Simulator XL (IES-XL) ASAP:

    % product-install-dir/tools/cdnshelp/bin/cdnshelp &

    If the "tools" directory is in your path, you can also simply enter the command cdnshelp.  However,…

    • 19 Feb 2009
  • Verification: Emulation vs. FPGA Prototyping

    Ran Avinun
    Ran Avinun

    There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market for both. The FPGA prototyping segment addresses mostly validation of smaller designs or a single IP while emulation…

    • 19 Feb 2009
  • Verification: Grey-Boxed Data-Path Approach Using 'when sub-typing'

    teamspecman
    teamspecman

    [Please join Team Specman in welcoming the first guest blogger from our user base: Ms. Kaberi Banerjee, a senior design & verification engineer based in Silicon Valley California]

    Fellow Specmaniacs (or should I say "specmites" – in alignment with the subject of bugs!), I recently had a very pleasant encounter with the all powerful Specman “when” sub-typing that I would like to share with you. (When subtyping is one…

    • 18 Feb 2009
  • SoC and IP: Denali MemCon 2009 Website Launched

    Denali Blog
    Denali Blog


    Denali MemCon Silicon Valley Coming June 22-25; Register now!
    Denali has just launched its website for Denali MemCon Silicon Valley, to be held at the Hyatt Regency in Santa Clara from June 22-25. Headlined with the theme, “Beacons of Innovation," this eighth annual event will host more than three dozen industry speakers and four panel sessions, and focus on those important trends that will lift the semiconductor…
    • 18 Feb 2009
  • Digital Design: Constraint Construction: What's Its Function? Part 2 of 4

    archive
    archive

    Part 2 - I/O TIMING: Talking Outside The Box

    It wouldn't be a chip or block if it didn't have to talk to something other than itself right?  We could always assume that every input arrives at exactly the same time, and every output has exactly the same amount of external delay.  The downside is you may never realize some of the more complex aspects of the I/O timing without digging a little further. Last time we…

    • 18 Feb 2009
  • Verification: Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi

    Adam Sherer
    Adam Sherer
    On February 11 Cadence announced that Adaptive Chips had adopted the Incisive verification solution using the OVM to improve its verification process.  I had the opportunity to "virtually" sit down with Amjad Qureshi, Vice President of Technology at Adaptive Chips, to ask him a few questions about his project.
     
    Amjad, can you tell us about Adaptive Chips?
    I am currently the Vice President of Technology for Adaptive…
    • 18 Feb 2009
  • Analog/Custom Design: Video Demo: Spice 2.0 - The ABCs of APS

    archive
    archive
    Designers have had ubiquitous access to powerful SMP/multicore systems for years but no analog / mixed-signal solution that could fully leverage them. And when dealing with large designs, fastspice and the accuracy loss it induced was often the only recourse. APS represents a new era for spice simulators not only because it's ultra efficient but also because it parallelizes all aspects of its work. Multi-day long sims…
    • 18 Feb 2009
  • System, PCB, & Package Design : What's Good About FPGA Capabilities in Capture? Download the SPB16.2 Release and See!

    Jerry GenPart
    Jerry GenPart

    With the SPB16.2 release, a few new FPGA enhancements have been added.

    In recent years, the design of FPGA and Printed Circuit Boards (PCBs) has become increasingly parallelized as opposed to the traditional sequential model.
    The basic symbol information such as pin name and pin number may be gathered from multiple sources. For instance, symbol information can be copied and pasted from the device user guide. This is not…
    • 18 Feb 2009
  • Verification: How to Save OS Boot Time In Your SystemC Virtual Platform With Save and Restore

    georgef
    georgef
    One advantage of using a virtual platform or virtual prototype over real hardware for embedded software development and testing is the ability of some simulators to save snapshots of their state. If your processor model is detailed enough, it might take several minutes (or even hours) to simulate booting the OS. If you save a snapshot of your simulation just after you’ve finished booting, each time you want to run your…
    • 18 Feb 2009
  • Verification: OVM Is The Safest Bet By 2:1

    Adam Sherer
    Adam Sherer
    One of the questions verification engineers will be asking as they head to DVCon in two weeks is "do I bet on OVM or VMM".  According to the poll conducted by Harry Gries in his Harry the ASIC Guy blog, you should go "all in" on the OVM because it is the 2:1 favorite.  Those are great odds!

    Over here at Cadence we were pondering the same question and started by estimating the world wide verification…

    • 18 Feb 2009
  • Verification: The Real Story on HLS With ANSI-C/C++ vs. SystemC

    archive
    archive
    There's a new post worth reading for anyone interested in the current state of high-level synthesis (HLS).  http://www.deepchip.com/items/0479-04.html, apparently posted by Mentor.
     
    The article highlighted the results of a worldwide survey that asked 1500+ engineers their reasons for considering/using HLS.  800+ engineers responded, overwhelmingly citing "faster time to RTL" and "faster verification…
    • 17 Feb 2009
  • Verification: SystemC TLM2 based Virtual Prototype Demo at DVCon

    Steve Brown
    Steve Brown

    DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group, and a TLM2 Modeling and Interoperability Tutorial, there's much to learn and contribute at the event.

    Cadence will have a booth and one of the demos is titled:

    "Virtual Prototyping with Metric Driven Verification and SystemC TLM2"

    It will be available from 2-4pm…

    • 17 Feb 2009
  • Verification: C-to-Silicon Does Not Require a Library Characterization

    TeamESL
    TeamESL
    One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis tools is its ability to directly read industry standards .lib files. By providing this ability an expensive library characterization which is required by other ESL Synthesis tools is avoided.

    This approach not only avoids an expensive library characterization, which only provides estimates of the component delays, but also has the advantage…

    • 13 Feb 2009
  • Verification: Blogger of the Quarter Award -- Thanks!!!

    jvh3
    jvh3

    Little did I know that when I accepted an innocent looking meeting propsal from my colleagues on the Blog Team I was destined to be the recipient of the quarterly Cadence blogger award today! 

    The scene: this "meeting" turned out to have more attendees than I expected, where my colleagues on the blog team arrived with a whole cast of characters behind them -- my management, our internal Communications specialist, and the…

    • 13 Feb 2009
  • Verification: New Blog series- Team ESL

    Ran Avinun
    Ran Avinun
    Cadence is well known for its leadership in system verification leveraging its HW-assisted verification market segment. Last year, we have expanded this segment offering, combined it with our System Software capabilities (focusing on Electronic System Level - ESL) into a larger segment - System Design and Verification. C-to-Silicon was launched as a new solution addressing the ESL design domain. In order to communicate with…
    • 13 Feb 2009
  • Verification: Exploring the Virtual Platform Part 4

    jasona
    jasona

    Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1, Part 2, and Part 3 of the series to get up to speed (hopefully soon before it becomes too difficult for me to provide links to every previous topic and too difficult for you to catch up).

    We will continue to look at the embedded software aspects of the ARM Integrator Virtual Platform. So far we looked…

    • 13 Feb 2009
  • Verification: Post-Show Thoughts on DesignCon 2009

    tomacadence
    tomacadence

    Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and I'm finally finding a few minutes to comment on the event. I have a soft spot in my heart for this conference; I think that I've presented something in some form at every show but one since it was called Design SuperCon way back in the mid-90s. I agree with Joe that this is not a major conference for advanced verification folks, but I…

    • 12 Feb 2009
  • Verification: Road Trip!

    jvh3
    jvh3

    on_the_road

    As at most companies these days, Cadence is doing what it can to minimize travel expenses wherever possible.  Consequently, whereas my business trips used to always involve an airplane in some way, these days myself and my colleagues fan out by car from our repective offices to visit customers.  Hence, this week I'm on the road -- literally -- driving behind the wheel of my own vehicle to call on a long time…

    • 12 Feb 2009
  • System, PCB, & Package Design : Focus Area: EDA Librarians - Manual Versus Automatic

    Jerry GenPart
    Jerry GenPart

    Nope - I'm not talking about automobile transmissions ...

    I'll continue my series on the SPB16.2 new product features in the coming weeks.

    I wanted to take a brief break and talk about, or more importantly learn from you, some of the basic techniques you use in constructing PCB library components. While this may appear to be a simple exercise in building parts for design entry, there are many facets to EDA libr…

    • 11 Feb 2009
  • Verification: Tech Pubs Tips Series Kickoff: Search for Single Character Words

    teamspecman
    teamspecman

    [Team Specman welcomes the Technical Publications Team to our blog]

    Effectively documenting feature rich, constantly evolving products like Specman, Incisive Enterprise Simulator XL (IES-XL), and Enterprise Manager is a challenge to say the least.  This gives rise to a corresponding challenge for end users: finding the info they need as quickly and easily as possible.  To help address both these issues, we on the "Tech Pubs…

    • 11 Feb 2009
  • Analog/Custom Design: Your Virtuoso MMSIM Portfolio 2009 Performance Outlook

    deana
    deana

    John Pierce, Product Marketing Director for Virtuoso Simulation application gives us some words of wisdom when it comes to getting the most from your simulation investment in 2009.

    John writes: “In 2008 your investment in Virtuoso MMSIM had tremendous returns:
    • Spectre ‘Turbo’ Technology,  MMSIM 7.0, provides 5-10x Performance SPICE was announced in April 2008.
    • SpectreRF ‘Turbo’ Technology,
    …
    • 10 Feb 2009
  • Digital Design: Constraint Construction: What's Its Function? Part 1 of 4

    archive
    archive

    Have you found yourself frustrated at the lack of some decent timing constraints?  Perhaps made critical floorplanning and placement decisions only to have them thrown out because someone forgot to mention a tiny detail in the constraints? Often times, the role of timing constraints is marginalized until it's just too late.  

    Instead of assuming the constraints are correct, and getting rid of the attitude "That's not…

    • 9 Feb 2009
  • SoC and IP: Memory's Recession: Actions and Realities

    Denali Blog
    Denali Blog
    Now is the Winter of our Discontent: Five months into a memory industry recession of unknown depth and duration, we have seen as many different strategies in action as there are companies.

    Some companies instantly anticipated the worst, and laid off substantial fractions of their workforce; others came to mostly the same conclusion after one or two months, but waited (considerately) until after the holidays to reduce…
    • 9 Feb 2009
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