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I'm not proud to admit that I reacted with envy to the news that Twitter just received a $1 billion valuation.  This story inspired further chatter claiming that if Twitter plays their cards right, they could achieve a $5 billion valuation before long.  That's right: this fresh new internet combination of CB Radio, bad-but-fun TV, and primary source news, which barely existed even 1 year ago, could soon be worth more…

In the SPB16.2 release of Allegro PCB Editor, there are two (2) new very helpful features (among the many others) that assist PCB designers with component placement - Component Alignment and Placement Replication.

Component Alignment

• You can now specify a Vertical or Horizontal alignment of symbols based on their body center.
  • There are no associated options.

• The feature automatically attempts to determine the axis to align…

[Preface: we interrupt the Specman 9.2 Preview series to notify you of an update to the popular Specman-Matlab shareware package. Long before the term "crowd sourcing" was invented, our Application Engineers created and continue to maintain the venerable Specman+Matlab package described in this article. Guest blogger and Field colleague Jangook Lee is the latest to have refreshed it for a customer in Asia to support…

After delving into lots of new features in the Virtuoso Schematic Editor, the Library Manager and the Help System, I'd like to turn to our old friend ADE (aka Analog Design Environment, or for those of us who've been around awhile, Analog Artist).  ADE is another one of those tools that you're probably using exactly the same way you've always used it because--well, because that's the way you've always used it.…

Eye masks let you specify the acceptable parameters for what an eye should look like in order to extract clock transmissions and high-speed data to buffer models. The current method of creating and saving eye masks is tedious. SigWave  has been enhanced to allow you to create eye masks that you can save in .sim files and view/edit when you display the waveform in Eye Diagram mode.

One current use model for creating eye…

Since your circuit always runs at low-power, your verification should too.  To get that "always-on" low-power verification, Incisive Enterprise Simulator (IES) uniquely verifies low-power behaviors natively.  In some cases that can result in tests that run faster with power analysis on than with power analysis off - engage the warp engine!

IES introduced the most comprehensive native-compiled, low-power…

Allow me to interrupt my blogging on MarCom and DAC to pose a question inspired by the back-to-school season:

You may recall a question was posted to Mike Stellfox back in February about the availability of a limited, student version of Specman and IES-XL for the student's personal computer (vs. the full Specman/IES-XLs our University program partners are licensed to run on official school machines).  Unfortunately, Cadence…

This new SPB16.2 feature allows Allegro AMS Simulator (PSpice) customers to simulate split parts as single components. The PSpice engine can identify different sections of a split part and simulate them as a single component by intelligently combining the sections into one single part. At present, the Split Part support is available only in the AMS-DEHDL flow.


Details

The Split Part feature has been provided to allow users…

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!]

[Team Specman welcomes back Yuri Tsoglin from Specman R&D to introduce one of “his” new features.]

Abstract
The current syntax of "when" struct member declaration explicitly includes the base (parent) struct name, in the context of which it is…

Have you ever gotten to signoff DRC and found that there was a small area where a filler cell did not get placed for some reason? Well, now there's an easy way to check for that with the checkFiller command:
    
    checkFiller -highlight true

   

To get rid of the highlights, do this:

    checkFiller -clearHighlight true

Another thing that is often found near the end of the design flow is missing power vias. You may have an IR-drop…

Does the union of verification automation and IT+source code management tools get you all misty eyed?  If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have you gushing tears of joy.  Specifically, this video shows IBM's Tivoli, Rational, and STG solutions married to Cadence's Incisive Enterprise Verification solutions.…

A few weeks before DAC, I started working on a blog post about the number of small EDA companies that remain in the functional verification space despite the tough economic times. My interest in completing the entry and publishing on this topic was increased by the number of small companies that I saw at DAC for the fifth, seventh, even tenth year in a row.

I used to observe that in 3-4 years most EDA startups were acquired…

Wait, don't run away!  In this case I really mean "Read The Fantastic Manual".  A recent comment by a reader prompted a spirited internal discussion here at Cadence regarding our Help system.  I suddenly realized it had been ages since I even looked at it.  Seriously, when was the last time you clicked on that "Help" menu at the top of your screen?

So I started doing some exploring and discovered that…

Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their trade show strategy -- his message is reproduced in full below.  Please post your comments here for the benefit of whole the community, or contact XJTAG apart from this forum via http://www.xjtag.com/company/contact.php

------
August 24, 2009
Subject: RE: UPDATE: please comment on XJTAG booth strategy at DAC 2009

Hi Joe

You have asked for my commentary…

[Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!]

[Team Specman welcomes Reuven Naveh from Specman R&D to introduce “his” new feature.]

Abstract
In Specman 9.2 we are extending the syntax of constraint declaration in a struct to support a user defined name and a string message in case the constraint…

In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls", a pair of sales models stationed in the booth of XJTAG, Ltd., a supplier of IEEE 1149.1 boundary scan development tools.  The surprisingly strong reactions to this classic trade show strategy prompted me survey our community about the propriety of the XJTAG Girls for a B2B show like DAC.  Since I'm not certain how persistent…

I'm taking a break this week from the technical type posts to say THANK YOU to the people who make blogging a success.

Of course, Blogging and Blogs are only successful if they are read and people post their thoughts and questions to continue a discussion. The PCB Design Community members - customers, Cadence, and industry folks - have been a terrific team in posting both in the Blog and Forums. Truly, it is the readers…

Co-Design … some are trying to do it with spreadsheets … everyone is talking about it.  But talk is cheap.  Can you really optimize a package footprint and a chip I/O padring such that that package and PCB costs can be minimized?

What if using a straight forward flow you could take the devices to which your chip needs to interface and place them on a canvass with your chip and package.  And then what if you…

The Design Entry HDL (DEHDL) usability improvements are many and significant in the SPB16.2 release!

The DEHDL product moves even closer to other Windows based applications, such as Capture CIS, Adobe Reader and Microsoft Office applications, in terms of the general usability standards. These changes provide support for common Windows commands and operations making Design Entry HDL more user-friendly and easy to use.

The…