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In the late 70's and early 80's system level PCB and Digital IC physical design evolved from manual Rubylith and Digitizing methods. If I haven't dated myself already with the terms Rubylith and Digitizing I know that I'll really be dating myself with my history at IBM.  While working for IBM in the General Products Division San Jose, CA during this period of time I used an IBM proprietary EDA application…

This past week, there has been a very interesting discussion on the "icu-pcb-forum" Email alias. Most of the people have migrated to our Cadence Support forums, but there are still a few that use the "icu-pcb-forum" Email alias.

The topic - Schematic drafting practices.

There are some "veteran" designers (several with more than 25 years of experience) posting their perspective and company practices…

[Team Specman welcomes back Methodology R&D leader Efrat Shneydor to present a 5 part series on performance-aware e coding guidelines.]

As all Specmaniacs know, the "e" language is flexible and powerful, containing many constructs that allow users to implement virtually anything. The downside of this freedom is that sometimes developers do not make the best choices when it comes to writing efficient code…

Let me be among the first in the Cadence "blogger corps" to welcome Richard Goering to the team. Anyone who has been involved in EDA in the past 20 years surely knows and respects Richard.

Personally, I spent about 10 of those years in Design, Verification, and CAD management, where I always read Richard's articles and columns for their keen insight into the tools I used or should consider using. The last 10…

At a purely technical level, Process Design Kits are fairly innocuous. They are used to enable custom IC design flows. A Process Design Kit (PDK) includes device models, schematic symbols, netlisting procedures and parameterizable cell layout generators. Physical verification rule decks and a parasitic extraction technology file are usually included in the kit. Quite a few of the tools used in custom IC, such as placers…

Every analog circuit design goes through some kind of electrical validation step before release to manufacture. The depth and breadth of this testing depend on the design itself, the end application and of course that all important deadline. When it comes to custom design, there is also an individual factor, as different engineers have different ideas on what validation is required. For example, on one end of the spectrum…

[Please welcome Markus Winterholer to the Team ESL blog.  Markus is one of the founding members of the ISX R&D team and is from Tubingen, Germany.]

At the Embedded World Conference in Nuremberg, Germany I delivered a presentation with the title "Metric Driven Functional Verification of Embedded Software" which caused a lively discussion started by Assistant Professor Dr. Winfried Dulz from the University of Erlangen…

You are probably wondering what Virtuoso has to do with the SATs and The Dark Knight.

Well, first of all, it has only been in the past few years (so this, obviously isn’t something I’ve had to do!), but today's high school students now have to answer essay questions on the SAT test, in addition to the traditional verbal and math sections. This is to test their writing skills in preparation for college. Writing skills…

In my previous posts on the DVCon 2009 panel on Software As A Service, or "SaaS" as it applies to EDA, recall that the main issues that came up were:

• Security (the focus of Part 2 of this series)
• EDA applications that can clearly benefit from SaaS
• Bandwidth needs
• Configuration control
• Dealing with and/or migrating legacy flows & data

Having addressed the security issue in my last post and/or putting security aside…

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen & Krishna, having "perfect correlation" for timing from RTL to Signoff can dramatically improve design closure and cycle time which…

Last night when I was waiting for my daughter to finish orchestra rehearsal (she is a violin player in the Greater Twin Cities Youth Symphony) I was reading an article in the latest issue of Communications of the ACM with the title "Is Software Engineering Engineering?".  The article covered topics are near and dear to me both as an engineer working in a company that produces software and as a producer of software…

One of the coolest new things in Encounter 8.1 is Bus Guides. I know many of you out there have probably looked at the results of a routing job and thought, "Why didn't it route this bus all together? It's all over the place!" Well, with bus guides, you can get your busses routed exactly the way you want. Here's how to do it:

First, you need to create a net group.

    createNetGroup myNetGroup -net {DTMF_INST…

In IC package design, it is becoming increasingly necessary to change a cline’s width in a given region, whether for signal integrity reasons or to allow all necessary traces to pass through a particularly dense region. This can be done to a limited extent through the use of constraint areas, glossing, and the change command.

However, depending on the nature of the desired width change, this can be difficult to achieve…

[Welcome guest blogger Reuven Naveh of Specman R&D]

What is the “constraints from above” problem, and how is it solved by Specman today?

The answer: “constraints from above” are stimulus generation constraints which have the following properties:

• They constrain a do-not-generate field or its descendants.
• The constraint is declared not in the type in which the field is declared, but at a higher…

Anybody watching Cadence these past couple years has probably noticed how we're pretty serious about investing in making tools for low-power design.  While most of the attention in the EDA industry up to now has been on how to optimize chip power consumption while working at the RTL/gate level, that is going to change drastically this year, where Cadence's focus will extend to optimizing chip power consumption while working…

Recently, a colleague here at Cadence created the image of an ecosystem, whose existence was necessary to sustain the ability to take custom design into new realms of ever increasingly small and complex technologies.  He of course was referring to Virtuoso.

He asserted that “…that it takes a village” to create custom analog IC’s as well. A “village” or perhaps better labeled “ecosystem”, is due to the very specific design…

Many design teams that use SystemC  are in various stages of evaluating TLM 2.0 – the Open SystemC Initiative’s transaction level library designed for modeling memory-mapped buses and on-chip communication networks. The new standard  takes us one step closer to creating an ecosystem where ESL models can interoperate across the boundaries of design teams, IP providers, and tool vendors. TLM 2.0 designs are much…