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We've gotten some good feedback about posts in this forum relating to dbGet and dbSet (the database access mechanism inside SoC-Encounter). I've been collecting interesting dbGet/dbSet lines over the past several months that I think are very useful. Some of these may be something you've wanted to do as well, or maybe they will serve as a starting point for a different idea or even a longer script. I gave credit to the…

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written by Advanced Layout Solutions.  In this post, Chris Halford discusses how his company works to ensure the PCBs they design meet requirments for voltage and temperature stability.  As Chris mentions, the challenge of managing power paths is complicated by the need to carve up power planes into swiss cheese like structres around high pin…

Well, I had good intentions of blogging from DAC, or at least summarizing my four days there when I was back in the office on Friday (July 31). But I returned to a very busy week of actiivties that got bunched up together partly because so many Cadence people were at the show. At this point, I can offer a look back rather than a real-time update. More of a repeat than a tweet, given that many of my fellow bloggers have…

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso) article this week before I go on vacation, but you know how it is when you're trying to get out of the office for a week.  Things just seem to pile up higher than usual.

So in place of the usual witty repartee and pithy comments, I'll leave you with some pointers to some of the Virtuoso webinars that have been posted on Sourcelink…

As much as the Design Automation Conference (DAC) is about demonstrating solution capabilities to potential customers, it is also about personal connections.  Reconnecting with old and current colleagues, and making new connections with people in the design community you haven't had a chance to meet before is as important as anything else you might do at DAC.  Maybe it was just me, or maybe it was because of Twitte…

One non-technology item that received an extraordinary buzz at DAC 2009 were the XJTAG Girls:

For those of you not at DAC, these sales models were effective in persuading passers by to trade contact info for a chance to win a portable GPS or iPod.  Of the 5,135 combined exhibits-only and conference attendees, I'd conservatively guesstimate that the XJTAG Girls scanned about 7,500 badges.

As I can attest…

No - we're not talking teeth, candy, and cavities here ...

Many customers have been asking us to support cavities inside of the Cadence IC Packaging tools for a number of years now. These are most frequently requests from companies trying to design leadframe packages (a technology that Cadence does not support within either the APD or SiP toolsets), though some have come from customers wanting to embed a die within…

I've told you in previous postings about some new features in Virtuoso IC6.1 which make it quick and easy to open cellviews you use frequently--namely the recently-opened files list (found in the CIW->File menu) and the ability to bookmark one or more cellviews (File->Bookmarks->Add Bookmark from any cellview window).

While these features mean that you can open that cell you work on every day with just a…

Specmaniacs,

With the start of DAC 2009, Team Specman is excited to finally be able to make public what we have in store for you in Specman/IES-XL version 9.2 this September.  Additionally, consider this post an open invitation to join the 9.2 beta program that officially starts next week on Monday August 3.

If you are at DAC, please seek out the Specmaniacs at DAC listed in our last post to learn more.  Otherwise, your local…

The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today.   Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one to debug when we scale the number of states, number of inputs, and consider asynchronous events.  While…

I'm looking forward to heading out to San Francisco next week for the 46th Design Automation Conference.  For my money, it's hard to beat San Francisco as a location for a trade show. Cable cars, Fisherman's Wharf, Alcatraz, San Francisco Giants baseball, Napa/Sonoma Wine Country...what a great part of the country.  And DAC itself is a great time in my experience.  You get to learn about all the latest things…

The following are the "must see" items for Specmaniacs lucky enough to get travel authorization for DAC 2009 (and/or who scored a cheap ticket on Priceline.com for a spur of the moment "vacation" to scenic San Francisco).

1 - Specman in the Cadence Main Booth (#3751, North Hall)
Given Specman's long support for ESL and TLM flows, Specman is featured in the TLM-driven Design&Verification suite…

In prior releases, Allegro PCB Editor does not provide the user the ability to place or make placement changes easily. New functionality to provide greater usability for component placement, alignment, replication of circuitry would greatly impact the time to get a design to fabrication.


The SPB16.2 Allegro PCB Editor introduces the 4th application mode; General, Etch Edit, IFP and now Placement available to Allegro PCB…

Yours truly will be at the big show next week, and I hope that all of you in the blogosphere will be able to sweet talk your management into letting you go as well. For those of you who have already won a golden ticket:

* By all means let's meet in person. When not in a customer or partner meeting, at various times I'll be on duty for Enterprise Verification at the main Cadence booth (#3751, North Hall), or supporting…

Some background info:
In a previous blog, I introduced:

• DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction.
• RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings. See “Part1: Using wreals to simulate Frequency Scaling for Dynamic Power Reduction” for details …

By now, you've probably seen that Cadence is participating quite heavily in DAC this year. Many of my fellow bloggers will be there, as will I. This will make DAC #22 for me, and I'm still looking forward to it...

(Parenthetical comment: I know that I'm dating myself in this post, but in the Internet Era anyone can easily search my name and see that I had my first IEEE publication way back in 1981. So can I indulge…