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Coplaner waveguides (CPW) are widely used in packaging, high speed designs and on silicon. These structures are now supported in Allegro PCB SI.

The figure below shows a typical coplaner waveguide. The important distinction for a segment to be a coplaner waveguide is a segment "W" surrounded by two large shapes. In order to detect coplaner waveguide segments while traversing a net, there needs to be a Shape window. The…

Welcome to part 5 of the Exploring the Virtual Platform series. This is probably (hopefully) the last post in the series related to the embedded software aspects of the Virtual Platform before I move to the hardware aspects of the platform and topics that are probably more familiar for Cadence users.

This post covers BusyBox - The Swiss Army Knife of Embedded Linux. Part 4 covered some details of how to cross compile…

Panels are some of the most popular sessions at many technical conferences. Getting a half-dozen opinionated, outspoken engineers to argue over a topic of interest to the conference attendees is clearly a good idea, and quite often it works as intended. I used to attend the International Test Conference (ITC), where the evening panels (with bottles of wine visibly being consumed by the panelists) drew audiences in the…

At risk of being lost in all the excitement of DVCon 2009 last week, my colleagues on the VIP Team announced a truly unique experiment, where the whole MIPI Verification IP product is available to try out now in the Xuropa Online Lab.  The important thing to note is that this is not some cheesy Flash demo, or a video of an AE giving a demonstration.  The Xuropa Online Lab is hosting the real product for you to run and interact…

Joe Hupcey has done his usual fine job of documenting DVCon (day 1, day 2, day 3) but I want to take a step back and summarize what has surely been one of the busiest weeks ever for the Cadence functional verification team. 

Our DVCon activities included a booth in the Expo, an OVM tutorial, an OVM lunch with three customer presentations, a panel on mixing simulation and formal, and several technical papers. 

Also, we participated…

Originally architected for multiple languages, the OVM is now available for all three standard languages used most commonly in verification SystemVerilog, e, and SystemC.  The e and SystemC libraries comply with the OVM 2.0.1 methodology and are available as open-source on OVM World.

All Languages in One Methodology - How?

The key to this all-for-one methodology is an architecture built from the ground…

Today I was able to cover a paper on "OVM-based Methodology for Low Power Designs", and the panel titled "Mixing Formal Analysis with Simulation: Why, When, Where, and How?"  Click here for some annotated photos.

Notes:
* Given there is much to say about the topic of Low Power in general, and OVM in specific, I felt authors John Decker and Neyaz Khan did a great job in compressing such an expansive subject…

ESL Virtual Platforms (systems or sub-systems) require heterogeneous libraries of TLM IP models that can interconnect. Indeed, the OSCI TLM2 interfaces appear to be the only viable solution to solve this interoperability issue. Moreover the IP you need is not always available (because it is a new IP or a custom IP or because it is not yet available from your 3^rd party provider). For whatever reason, you have…

Checkpoint Restart for Digital and Mixed Circuits will allow PSpice users to set checkpoints while doing a transient analysis for digital and mixed circuits, saving all the transient information onto the disk and then allowing users to restart the analysis from any of the saved checkpoints.

The CheckPoint Restart feature lets you save the state of a transient simulation at different moments as Checkpoints. One can specify…

Here are some pictures from DVCon 2009 Day 2, focusing on the OVM Case Studies lunch, some panel discussions, and a few more snapshots from the show floor click here.

Notes:
* The OVM Case studies luncheon showed a surprising variety of use models and applications, with multi-language interoperability under the OVM umbrella being a key factor in each of the very different projects outlined.  (Be advised that the photos of…

As an Applications Engineer, the first demonstrations you deliver of a new technology are always the most interesting.  The questions you receieve are all over the map and your skills in thinking on your feet are put to the test.  Personally, I really enjoy this learning phase and as I was putting together this screencast, I was reminded of the first demo I ever gave of First Encounter back in 2001.  The primary question…

SystemC is the most common language used for modeling transaction level (TLM) behavior of hardware. From the beginning of TLM users have been exploring how to perform functional verification at the fast TLM level, and hopefully reduce functional verification at the RTL level. The timing might have been a bit premature and theoretical, since it's only very recently that the majority of the market has adopted sophisticated…

Hi All,

With the release of the OVM-e library, there are now many new features available for users to take full advantage of.  I would like to discuss one new feature that, when introduced into a users environment, allows for much greater automation and control over a given simulation run.

The e language has had built-in test phases for close to a decade now.  Users of e will be very familiar with the following phase methods…

As promised, here is my photo blog of Day 1 of DVCon, focused on the OVM Multi-Language tutorial and the show floor.  While I've added descriptive captions to the photos, here are some quick takes:

* Adam, Brett, and the others at the OVM Multi-Language tutorial reported that the session was very interactive, with a lot of great Q&A that indicated a clear need for this enhancement to the methodology.

* FAQ: how was…

If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification, the Allegro PCB team has a number of ways we can help.

First, be sure to attend or watch a recording of the webinar planned for March 11 where we will walk through some of the latest technology built to address high speed memory interface design.  You can register…

More of our customers are using Incisive for transaction level modeling (TLM) and functional virtual prototyping, analyzing design characteristics before committing to RTL architectures. SystemC is the design language of choice for most of these users, because it is an industry standard, and Incisive provides important connections into the RTL verification flow. Similarly important is the employment of an advanced testbench…

Many of the messages published by Gabe Moretti in his recent EETimes article resonate very well with Cadence strategy. 

Specifically:

• Evolving standards are important with SystemC and TLM becoming the center of the ESL world
  • Cadence supports SystemC with its Incisive Enterprise Simulator and C-to-Silicon high-level synthesis
• The need to connect the "ESL" world into the "RTL" world in order to migrate this …

Specmaniacs and other eRM & OVM users,

Today we offically released the eRM 3.0, er, we mean the "OVM e" library as an open source library: Cadence Enhances Verification with Greater Flexibility

As you also may recall, in parallel Cadence has already donated to the IEEE 1647 Working Group all of the remaining language technologies that underpin eRM that didn't make it into the original IEEE 1647-2006 or 1647…

For those of you that will not be able to make it in person:
So you can follow the action at home, when not on duty in the Cadence booth I'll be snapping pictures for a daily DVCon photo blog along the lines of what I did for CDNLive San Jose last September. (Recall my reports from CDNLive days 0, 1, 2, and 3).  I'll also be bringing my video camera (but one thing I'm learning is that editing video takes a lot more…

IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode.

One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very simple to achieve !!! So, I thought of sharing it here.

Viewing the combined help for IES-XL product: As long as…

[Welecome back the Tech Pubs team as guest bloggers]

Sometimes you just need a little help -- fast.  Like right now; or even yesterday.  Here is the UNIX command to get you the online help you need for Specman and Incisive Enterprise Simulator XL (IES-XL) ASAP:

% product-install-dir/tools/cdnshelp/bin/cdnshelp &

If the "tools" directory is in your path, you can also simply enter the command cdnshelp.  However,…

There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market for both. The FPGA prototyping segment addresses mostly validation of smaller designs or a single IP while emulation…

[Please join Team Specman in welcoming the first guest blogger from our user base: Ms. Kaberi Banerjee, a senior design & verification engineer based in Silicon Valley California]

Fellow Specmaniacs (or should I say "specmites" – in alignment with the subject of bugs!), I recently had a very pleasant encounter with the all powerful Specman “when” sub-typing that I would like to share with you. (When subtyping is one…