Community

When I first hired on as an AE at Cadence (eighteen years ago!), I realized how many great features were available in the software which I did not know about as a designer.  So much of my time was spent on design and verification, there was little time to explore all the capabilities of the software.

With that in mind, I'd like to share a demo of a new signal comparison utility, SimCompare.   You can do interactive comparisons…

Just a short post this week, as I've been quite busy recording videos for some of our Virtuoso Platform Webinar Series, the last of which, covering Spec-Driven Design, airs Tues. June 30.

Recordings of this and past webinars can be found here. (If not posted there yet, they will be available soon).  They've called these the 300-series webinars, a college course numbering analogy to let you know that you'll be getting…

In "Spectre RF by any other name ...", a non-RF application for Spectre RF's periodic steady-state analysis was introduced. An example of using periodic steady-state analysis [PSS] to simulate the dynamic performance: THD and SFDR, of a switched...

Two capabilities in SystemVerilog allow for the creation of a module that can produce a sine wave as an output: the ability to pass real values through port connections and DPI.

Obviously, to produce a sine wave, you need access to the sin function. This is where DPI is handy to add the math functions to your simulation. Here is an example of a package I created to contain the math functions:

To allow for increased solvability, some constraints that were previously uni-directional with the old “Pgen” generator are now treated by IntelliGen in a bi-directional manner by default.  This behavior dramatically improves solvability and gives you a lot more freedom in writing and layering very complex constraints. 

However, if you are coding with a Pgen frame of mind there is one case where the results…

In order to complete a brand new design on time, it is an important factor to effectively reuse existing design modules. The use of an automatic optimization quickly and easily increases design reuse efficiency. The following figures are examples of a source layout and an optimized result made by Virtuoso Layout Migrate. Virtuoso Layout Migrate optimizes a design automatically by satisfying design specific constraints…

Processor-based FPGAs represent 40% of all the design starts today and will rise to > 50% in 2011 (Gartner, March 2009).  In the same time period, the number of ASIC-based SoC starts is about an order of magnitude smaller. Sure, many of the FPGA starts use 8-bit processors and have a small amount of logic, but the high-end SoCs -- represented by product families such as the Xilinx(R) Virtex(R)-6 and Spartan(R)-6 --…

Check out Hemant Shah - Product Marketing Director for Allegro PCB Products - highlighting the new FPGA System Planner (FSP) product from the Cadence Silicon Package Board (SPB) division at the recent CDNLive! EMEA event.

You can watch Hemant from the event:

Available in two forms - Allegro FPGA System Planner and OrCAD FPGA System Planner - this new technology…

I apologize for the Internet slang in the title (urbandictionary calls OMG "the most irritating piece of chatroom vernacular in existence"), but I couldn't resist.  Ever since IC6.1 came out, it seems like every other question gets answered using the three-letter acronym (that's TLA for those in the know), RMB.  RMB to open an assistant, RMB to do this, RMB to do that.  If you can't find it anywhere else…

On June 10, Cadence issued a press release that mentioned “…decreasing the level of investment in the manufacturing side of DFM” as part of restructuring activities. Since that announcement, some in the press and analyst community have published their interpretations of the actions. A few of the published items do not accurately describe the actions that were taken, and we’d like to set the record straight. …

Team Specman is about to start a project to refresh the e/Specman Quick Reference card included with every Specman/IES release. (While the basics of the current card are OK, we concede some of its content is getting a little long in the tooth). Hence, please let us know your preferences about what we should edit, add, or subtract from the next version of the card in the comments below, or contact us directly offline.

For…

Starting June 23, 2009, Cadence technical experts will host a series of technical webinars on myriad of topics. During this free webinar series, you’ll discover possible solutions and best practices to overcome the challenges you may be facing today or ones you’ll soon be facing. Learn new applications and methodologies, ask questions, and follow up with our technical experts after the event to continue the…

Something seems to have changed in the Synopsys VCS simulator; the Web2.0 world is buzzing this week about the OVM running on VCS. We first saw a post on the LinkedIn "OVM Professionals Network"on Monday June 15.  Today we saw a more detailed posting at IntelligentDV specifically stating a released version of VCS that will run the OVM.

For nearly two years we have talked to many VCS users who wanted to access…

Recently I had the honor of delivering the introductory section of a detailed demo on "Metric Driven Verification 101" given by my colleague Nick Heaton, an Architect in our Verification Solutions organization.

Specifically, after a few introductory slides by yours truly set the stage, in the video Nick shows in detail the methodology behind metric driven verification ("MDV"), and how it improves…

Since posting an introductory article and demo on AMIQ’s “DVT” integrated development environment (IDE), AMIQ has seen a spike in interest in the tool (yeah!)  Given the particular interest being shown by Specmaniacs, AMIQ has forward us the the following tech tip about how you can point to Specman’s HTML docs, AND how you can search through the docs from inside DVT itself.  (Recall that DVT is…

Our product marketing manager for Allegro PCB products, Hemant Shah introduced the FSP product in his Blog post - Innovative Approach to Optimized FPGA Pin Assignment


For an interesting interview about the new FPGA System Planner (FSP) product, please read the details here.

Here are some "take-aways" from Hemant's interview that I found noteworthy:

• Our customers are leveraging the power, design flexibility…

I keep my toothpaste in my bathroom.  I keep the paprika in the kitchen.  I keep the band-aids in the bathroom near the living room.  Two points here.  First, I keep the tools I need near the place where I do the activity for which I might need them.  Second, I try to always keep things in the same place so I know where they are when I need them.  Sounds sensible, right?  Dinner would never be ready on time if I had to keep…