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And the new features list just keeps going on and on - it's terrific!

In the SPB16.2 release, the Allegro System Architect (ASA), and System Connectivity Manager (SCM) products have been enhanced to provide Differential Pair Swapping capabilities that interface with the Allegro PCB Editor product.

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1 and Part 2 of the series to get up to speed.

Today's topic is debugging. One of the great things about a Virtual Platform is the ease of debugging code running on the platform. In the first 2 segments we demonstrated how to compile the Linux kernel and run it on the ARM Integrator platform. As…

There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager for Virtuoso APS that elaborates on parallelization technology and how it's been used to deliver improved performance in Virtuoso APS. Take a look, click here!

This week the "DesignCon" show is in town (<= 10 minutes from the Cadence campus at the Santa Clara convention center), so I couldn't resist the opportunity to check out some of the speeches and exhibits.  I'm happy to report that my curiosity was rewarded -- here are my notes along with some photos:

* First, full disclosure: Cadence -- both Corporate and Chip Estimate -- have modest 10x10 booths on…

Allow me to direct your attention to a most welcome article in EDA DesignLine written by Gabe Moretti:

Title: [End] EDA bashing
http://www.edadesignline.com/213000305?cid=RSSfeed_EDAdesignline_edadlALL

In a nutshell, the article argues that general, blanket criticism of the EDA industry -- "EDA bashing" -- is unhelpful to say the least.  I couldn't agree more, and I assure you that my concurrence is not motivated…

Team Specman has been doing a great job supplying nifty tech tips and other useful information about using Specman. Recently, they sent us R&D types a request for new topics to cover. I quickly took them up on it and supplied a post about how to interactively debug when using the Specman Co-Verification Link. Joe asked if I would follow up to clarify the differences between CVL and ISX. These two things are slightly…

[Join Team Specman in welcoming guest blogger Jason Andrews.  Jason is a recognized hardware-software co-verification expert (he's written books on the subject!) and a fellow blogger]

One of the long-time features of Specman is "CVL". It stands for "Co-Verification Link", but is somewhat misnamed. CVL connects a host compiled C program to Specman via a network socket. This feature enables e methods…

I wanted to share some experiences I had with SpectreRF-Turbo and Parasitic reduction on a recent large benchmark. The things I learned may be helpful to anyone who wants to get the most out of turbo and parasitic reduction.

Available in MMSIM7.0.1 and...

One of the new features I mentioned in my previous entry on 3 Reasons You'll Want to Download Encounter 8.1 is the Foundation Flow. Have a look at this screencast for a demonstration of how to take an existing design loaded in the system and quickly get up and running with the Foundation Flow:

If the video fails to embed, please try here.

The steps described in the video are:

1. Load a design into Encounter
2. Select…

I've been having a lot of fun with power switch cells lately. That's a whole other story (and perhaps a future blog entry), but in my experiments I was able to use dbGet in some neat ways. I posted previously about getting started with dbGet here.

After you've experimented with dbGet for a while, the natural next step is to start using it in scripts or pieces of code.

The scenario: All of my switch cells were…

Cadence will present SpectreRF Noise aware PLL flow latest enhancements at the DesignCon 2009 conference, based in Santa Clara . In the paper "Noise and Jitter Analysis for PLL-Based Frequency Synthesizer", we fully describe SpectreRF flow and provide...

It's here! It's really here!!!

I've spoken with many customers over the past several years and so many have requested an automatic Table of Contents (TOC) generator for Allegro Design Entry HDL (DEHDL).

In most of the designs you construct, the first sheet (or sheets) of the schematic design contain a table of contents (TOC). The SPB16.2 release contains the functionality for creating and automatically updating…

While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message:

Error! integer overflow

File: ./test.vhd, line = 13, pos = 11

Scope: :$PROCESS_000

Time: 10 FS + 0

./test.vhd:13 i := i - 1;

Incisive is probably the only simulator to report such error condition. The only other popular VHDL simulator was not able to catch/report this condition, when…

Specmaniacs and Other Trailblazers,

The latest edition of the 'ClubT' newsletter is now posted here, and once again there is exciting news around e, Specman, and Verification.  Articles include:

* Have you heard of OVM e?

* Incisive 8.2 Technology Update

* Verification IP Portfolio E-x-p-a-n-s-i-o-n

Note: We did not send a newsletter out last October since we ran the 'ClubT' events then (with over 200 total attendees…

Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification.  In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel,  Do It Right or Do It Over? Signal Integrity Engineers in the Era of Highly Compressed Project Schedules where industry professionals…

Those of you attending DesignCon in February should stop by the Cadence booth to see the latest integration of PakSi-E in SiP SI.  This integration not only supports signal integrity, but also there is new package power integrity technology.

We will also be showing techniques where Package-on-Package designs can be created, optimized, and analyzed.

I also hope you will drop by the Multi-Die Chip/Package Co-Design for SiP…

MMSIM 7.1 has just been released!

The following IC release GUIs support the new MMSIM7.1 features:

IC5.1.41.500.5.129 (However, USR6 or later is strongly recommended)
IC6.1.1 ISR65
IC6.1.3 ISR5
And later subversions.

In my last blog, I asked all of you to send me your design innovations. Thanks for your over-whelming response…and keep the emails coming in. And what better way to start the New Year than to talk about ST Microelectronics and its innovations!
 
I’m pretty darn sure that most you have heard about the company. But for those of you that haven’t, ST Microelectronics is a global leader in developing and delivering semiconductor…

Here in Cadence Product Marketing, we're still recovering from our very busy annual sales conference last week. Of course, I can't say much about what transpired there but I do want to comment that functional verification was a hot topic. In my many conversations with our field team, two trends were clear.

The first is that customers just can't afford to re-spin chips in the current economic climate. With the…

It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design and its challenges was published recently by SCD Source and written by the popular long time industry writer Richard Goering (click here to read).  3D-IC when combined with…