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The 7.1 release of MMSIM is scheduled for mid-January. There are many exciting RF enhancements that will be useful for RF designers.

1. Three new RF analyses using the harmonic balance engine, have been introduced to make the Spectre RF easier to use: 

Some very helpful new features for Differential Pair support are available in in the SPB16.2 release.

A major enhancement made to Diff Pairs in the SPB16.2 release involves the use of Regions to define Diff Pair Line Width and Gap. Prior to 16.2, a change of line width/gap on the same layer was controlled with the Neck Width and Neck Gap parameters. Restrictions associated with the necking implementation…

I knew this functionality existed, but I hadn't really put it to use until yesterday. It saved me a lot of time, so I just had to share. Here's the situation I found myself in:

LVS showed that I was missing vias to a small handful of my power-switch cells. Due to the structure of the cell, we had to make a modified copy of the LEF to get the exact via structures we wanted when we initially put in the power grid…

Having summarized the main verification technology-specific observations that the "Trailblazer" team saw in 2008, which to recap were:

1 - 1 billion logic gate chip roadmaps are here
2 - True "Metric Driven Verification" (MDV) starts to evolve from CDV
3 - The "language war" is over -- all languages won!
4 - Pre-silicon HW/SW co-verification became too important to ignore
5 - Analog+Digital verification…

Hardware verification has evolved into keeping track of a pile of different types of coverage. There is line coverage, expression coverage, toggle coverage, assertion coverage, finite state machine coverage, and functional coverage. There are probably more types I'm forgetting related to low power or analog or something else.

Software verification primarily utilizes code coverage. Tools like GNU gcov and others can…

Two of the most important parameters for accuracy are:

(1) maxharms

(2) oversample


maxharms:

The accuracy of HB is greatly dependent on the number of harmonics chosen. As a general rule, you should simulate with with maxharms [5 3] and (if memory allows...

Specman's new Generation Engine, "IntelliGen", adopts an entirely new generation scheme compared to the previous engine, "Pgen".  It groups fields which are related via constraints into a Connected Field Set (CFS) and automatically determines the order in which all CFSs must be solved. All fields of the CFS are solved together (e.g. several fields can be reduced in one reduction step).  For…

Many users ask, "How do I instantiate a netlist into my schematic and simulate with spectre in ADE?"

To instantiate a subcircuit (netlist) in your schematic and simulate with spectre in ADE you need to create a cell with a CDF parameter 'model...

The SPB16.2 PCB SI release now contains the Electromagnetic Solution 2D Full Wave field solver (EMS2D).

High density interconnect on PCB and packaging designs with signal switch rates over 5 Gpbs require model characterizations that can support frequency ranges from DC up to THz. Within this wide spectrum, electrical resonance, oscillation, signal dispersion and EM radiation are all likely and must be accounted for. Static…

Before I dare take a stab at adding to the many predictions already made for 2009 (like those in EE Times and SCD Source), allow me to share with you some of the main verification technology-specific observations that the "Trailblazer" team saw in 2008:

1 billion logic gate chip roadmaps
As noted in a previous post, SoCs with over 1 billion logic gates are now on the drawing boards of customers around the wor…

First: Happy New Year, Specmaniacs!

Much like the rivarly between the New York Yankees and the Boston Red Sox (or if you prefer, ManU vs. Chelsea, or the Tokyo Giants vs. Hanshin Tigers, or [insert a cricket example here]), Specmaniacs have been divided into two competing camps, with one group favoring "when inheritance", and the other "like inheritance".

Before R&D and others from Team Specman elaborate…

Happy New Year everyone! I hope you all had a restful, enjoyable and healthy holiday season. I trust that you're all going through a mountain of E-mails this morning and trying to get back into the swing of working. If it helps, give yourself permission to merely get caught up on things and if you're able to solve even a single technical issue you'll earn extra credit in my book. :)

As advetised by my colleague…

One endless source of neat little tricks is the Reflection API built into Specman.  You can implement pretty much any utility you dream of with it, and quite intuitively.  Here is a case study:

Have you ever agreed with your peers on the best coding conventions, and then saw the conventions decaying over time for lack of enforcement?  Specman/e's Reflection API lets you implement pretty much any sort of static checks on your…

In my last few posts, I was explaining our focus here in Cadence Verification on creating the OVM to enable an industry wide VIP eco-system, and trying to make verification more of a closed-loop process with our metric-driven verification methodology.  In case you missed the announcement about expanding our VIP portfolio back on October 15th, we just made it a lot easier for you to experience the benefits of the combination…

Hi All,

It always amazes me to see just how many Specman users make use of the interactive command line to load files, set breakpoints, run sims and debug.  I just wanted to update all you command line gurus that, as of the 8.2 release of Specman, a new switch "-e" turns on some cool editing features that you can use directly from the specman command prompt. 

If you use add the -e switch when calling specman:

%…

I and the rest of the Cadence C-to-Silicon Compiler (CtoS) team were thrilled yesterday to learn that EDN selected C-to-Silicon Compiler as one of the "Hot 100 Electronic Products of 2008".

http://www.edn.com/article/CA6622869.html

How about that,  John Cooley!!   www.deepchip.com.

Why does the launch of CtoS in 2008 represent a significant EDA industry milestone? Very simple.

HLS has been the "holy grail" of EDA for…

Last month I had the pleasure of attending a DV Club lunch presentation on analog verification (recall my report on the presentation + comparison to the Trailblazer program).  Consistent with all past DV Club lunches I came away more informed about the subject matter, and with renewed contacts in my local verification community.  Given these positive experiences, I'm happy to relay that the DVClub people have just published…

Even though 2008 will probably go down in history as the year of Doom and Gloom we can find a Ray of Hope here and there. 2008 was a good year for ISX. We entered the year with just a handful of companies using the technology and we will exit with many successful projects completed and new projects starting all the time. The launch of the new cadence.com is also a Ray of Hope. It has been a great experience for me to post…

The other day I saw some posts to the Yahoo Specman group regarding e ports. The last one in the thread asked for some introductory information on ports which I thought might make a good topic for my entry today.

As I was researching what I wanted to include in the post when I came across some related content in Chapter 7 of the Usage and Concepts Guide for e Testbenches manual in the Specman help.  Rather than ramble on…

As a verification engineer, I have always found creating coverage code to be one of the more time consuming tasks to actually execute on for two reasons:

1. While the general process of coverage creation is conceptually simple; in practice, actually figuring out what to can turn out to be more difficult then first anticipated.

2. Sitting down and actually coding all those coverage points can become somewhat tedious. This…

As the 2008 year comes to a close, I wanted to say Thank You!

Thanks to the hard working Cadence people who experimented with new ideas about the Cadence web site, polished those ideas, and included blogging to allow another format for customers and Cadence individuals to extend discussions on EDA, design techniques, and new technology topics.

Thanks to my Cadence friends. It has been a tough economic year for the world…

The irun utility provides a use-model to run simulations with Incisive Simulator in a simple and consistent manner.  The main benefit of irun is that it can simulate the multi-language design & verification environments in a single step by simply specifying all input source files and options on a single command line!!

The following demonstration shows the use-model with real examples:

If the video fails…

The SPB16.2 release now has new MOSFET device Model BSIM4 Support in PSpice

PSpice designers had been requesting support for the BSIM4 Mosfet Model. The BSIM4 model addresses the MOSFET physical effects into sub-100nm regime. It is a physics-based, accurate, scalable, robust and predictive MOSFET spice model for circuit simulation and CMOS technology development.

BSIM4 finds wide application in RF circuits since it's a…

Fellow blogger Joe Hupcey passed along a link covering the recent launch of the BlackBerry Storm. It seems to follow a familiar trend in consumer electronics: great idea, nice product, but the software seems slow and buggy. People send me these articles as if I'm supposed to do something about the situation. The article mentions a specific corner case where the music volume increases when a call comes in, and how Verizon…