Community

In an announcement concurrent with Semicon West 2008, Shocking Technologies has announced their Cadence Connections membership.  Take a look at the announcement and find out more about how Cadence Allegro PCB and Package designers can benefit from Shocking's rules and materials to safeguard their products from electrostatic discharge (ESD) dangers.

http://www.shockingtechnologies.com/pdf/Shocking_Cadence_Press_Release…

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in creating and re-using system-on-chip IP.  C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. 

C-to-Silicon Compiler automatically translates and optimizes abstract behavioral…

Inductors, transformers and transmission lines are critical components in any high frequency integrated circuit. Conventional electromagnetic tools used for the design of these components are difficult to setup, require electromagnetic expertise and are not integrated in IC design flows.

Traditionally, specialized modeling teams work hard for several months to design, fabricate and characterize a limited set of inductors…

Hello and welcome to the new Cadence community site, and my first blog post. You will see me here from time to time posting on topics and trends in the Power Efficient Design and Low Power Design area -- and most importantly, how we as a community can play a bigger part in ensuring your success.
 
If you have any topics you would like to see me cover, please feel free to leave a comment or send me a private message.

For my…

What's Good About Differential Pair Support in ASA?

Quite a bit actually!

In the SPB16.0/SPB16.01 release of the Allegro System Architect (ASA) product, there were several new features added for Differential Pair Support. You can certainly read the details in the new Cadence Help utility (which is also new and improved in the SPB16.0 release), but here are some highlights -

• Setup options for identifying user…

The EDA industry been doing system level design and verification for years; we just haven't been doing it very well.  Most all of us do hypothesize about what might be the ideal configuration of hardware and software to deliver our application in a cost effective way.

However, becuase there are so few tools we can use to test our hypothesis, we are soon reduced to taking a leap of faith in to commit to a particular…

Verification consultant Brian Bailey recently started blogging for Chip Design Magazine. One of his first posts was to define verification. He did a great job and I encourage people to read over what he wrote.

What you realize when you read his post is that verification is not directly related to two other topics that are often discussed as part of verification. These topics are important to verification, but are not verification…

Greetings!

My name is Steve Lewis and I'm a product marketing director working in the custom design area within Cadence. 

I thought I'd kick off this blog with a brief introduction. I've been with Cadence for almost 18 years, with three years additional experience working at Daisy CAE systems, a pioneer in the EDA field.

This blog will cover a wide range of topics related to analog and custom digital design…

Ordinarily chaos is bad thing.  Yet like it or not, the world your SoC lives in is in complete chaos -- your chip will see all sorts of unexpected stimuli and unimagined use cases over time, which can lead to end users finding the bugs you missed.

The most frequently viewed forum post in the old cdnusers.org "Digital IC->Floorplanning, Place and Route" forum initially started off as a seemingly simple inquiry: "Can CTS Stop Tracing on Hierarchical Module Ports?"

From that one question came a number of suggestions and discussion about using First Encounter (FE) Clock Tree Synthesis (CTS) LeafPin and LeafPort constructs and whether they could…

With all of the press and interest from customers adopting it, I am sure most of you have heard about the OVM (Open Verification Methodology), which is jointly developed and supported by Mentor Graphics and Cadence.  If you haven't heard about the OVM, you can check out the OVM World site to read all about it.

The main focus of the OVM so far has been on providing a testbench methodology and class library for SystemVerilog…

It has been said many time that SPICE, the analog engineers tool of choice, is virtually the same as it was 20 years ago, while digital engineers have been happily zooming up the evolutionary chain. There have been a number of attempts to prod analog designers into closing the gap with the introduction of behavioral modeling languages, and more abstract system modeling solutions. However, they are not widely adopted…

At the recent Design Automation Conference (DAC) in Anaheim, Calif., Cadence did not have a big booth but we were involved in many different activities. The most fun for me was the first "OVM World Summit" -- a meeting for users of the Open Verification Methodology (OVM). Cadence co-sponsered the event, which drew more than 70 attendees from a wide range of companies.

After introductions, three hands-on OVM…

There's a great issue of Xrosstalk magazine out there that talks about algorthmic modeling for high speed SerDes channels.  Cadence as well as other EDA companies give their take on the subject. 

Here's a link to the articles:

http://www.xrosstalkmag.com/images/magazine/xrosstalk_magazine_june08_final.pdf

What are your thoughts?

I'm curious with the availablity within DEHDL (ConceptHDL) of customizing the menus, toolbars, and softkey assignments, how many designers or site adminstrators customize their environment. Do you just add a few menu items or minor adjustments to the toolbars, or do you do quite a bit of customization? How much do you find it improving your efficiency using the product?

There are several designers who take advantage…

Simulation acceleration and emulation technology has been commonly used to run faster large blocks and system level configurations and to verify software against very fast and accurate RTL hardware model. With current system design capacities in the multi millions gates, simulating these designs at 100 -100,000 times the speed of a simulator provides already a huge benefit to system verification teams across the globe…

While I've attended a few Cadence Corporate User Group events over the past years, as well as originated the local Cadence North-Central User's Group (CNUG) here in the Chicago area (oh boy -- that was some time back...), I'm very excited to be attending this year's CDNLive! event in San Jose this coming September.

I'm hoping to meet many customers using the SPB products - the veterans who've I've worked…

A few years back, I was considering that the lack of an integrated design solution (tool flow) was the reason that SiP design was an "expert engineering" process -- and why it was not adopted more widely despite its benefits over SoC integration for a broad range of applications and markets.

However, since the initial release of our SiP solution (http://www.cadence.com/products/sip/index.aspx) a while back, and…

On June 16 2008, Cadence introduced a new Electromagnetic (EM) solver technology to address the challenges of verifying wireless integrated circuits implemented in advanced CMOS process nodes. You can read the press release here.

How is this going to help the RF designer?  Virtuoso® RF Designer brings a fast planar 3D EM solver to the designer's desktop. With its NlogN speed (where N is the number of unknowns), higher…

Take a look at the article linked below, titled: "ESL handoff: closer than you think."

It's by Michael "Mac" McNamara, a colleague here at Cadence -- and a fellow blogger.

Read the article here. Share your thoughts below.

One of the best books I read this year is called Dreaming in Code by Scott Rosenberg. I spotted this gem at the local public library sandwiched among some old books about Visual Basic and how to use Microsoft Office. The subtitle "Two Dozen Programmers, Three Years, 4.732 Bugs, and One Quest for Transcendent Software", definitely caught my eye. It is now available in paperback and is well worth the minimal cost.

As…

Once upon a time semiconductor companies produced a chip, made a data sheet, showed the data sheet to customers, provided samples for customers to try, and followed up to see if the customers wanted to buy the chip.

That was then, this is now. In today's SoC world, semiconductor companies must not only produce chips, they also need to put the chip on a board and develop all of the representative software for the application…