Community

One other question that you might ask is, this approach works for bipolars but what happens when you need to characterize a MOS transistor. Nothing changes, use the same testbench and measurements, see figure 1. In this testbench a MOS transistor is being...

Cadence OrCAD Capture is integrated with PartMiner. As a long time EDA librarian over the years, I'm always keenly interested when technologies are made available that assist us in efficiently developing components and component data that designers use in the daily schematic capture tasks.

According to Steven Kamin, Group Director for PCB Product Marketing at Cadence, "Electrical engineers face sizeable challenges in…

OK JL, one more marketing post, but this is a good one and even hints at technical content to come.  :-)

Y'all may have seen that Mentor and Cadence announced that the OVM Advisory Group (OAG) has been up and running since February this year.  You may notice that Mentor and Cadence are not members of the OAG, but rather receive their guidance.  This first step makes OVM more independent while still tapping the development…

So, what's good about Capture-CIS Digi-Key Integration? Quite a bit actually! This just in: "OrCAD Capture CIS customers now have access to the wealth of engineering data offered in the Digi-Key part database." This is some nice technology that combines engineering data with enterprise information.

Read this press release for details.

Cadence® Design Systems’ OrCAD® Capture CIS…

Are you planning to attend this year's CDNLive! Silicon Valley 2008? Please leave a comment below if you're going to.  Hope to see you there!

If the embedded video does not appear above, please use this link:
http://www.viddler.com/explore/RobertDwyer/videos/1/

Links mentioned in this video:
Register for CDNLive! 2008 Silicon Valley

In his latest blog post Space Exploration ... design is, Grant Martin said that ESL synthesis is an important tool in the overall design flow. Grant also mentioned that this capability opens new opportunities for the development of design space exploration tools that link into the various implementation flows from various vendors and for various alternatives and allow people to really explore space effectively.

For a…

To follow-up on my previous post on the techtorials, I'm posting some photos from some of the sessions last week and this Tuesday.  With a ratio of 80% attendance/registered (in North America the average for these things is typically 50%), it's clear that interest in coverage driven verification (CDV), its big brother metric driven verification (MDV), and the supporting methodologies like OVM and eRM is very high.…

Often, when engineers set out to build something, the result is different from the original plan. Recently, I was reading a book titled Founders at Work: Stories of Startups' Early Days. One of the chapters is about the founding of Hotmail, one of the first e-mail websites. The founders set out to build a personal database to use as a back-end for websites. When they got to work on it they had trouble communicating with…

Open things are just curiosities until the ecosystem figures out how to turn them into money.  Java and Linux are good examples of that.  When they first hit the "open" space, they were interesting technical solutions to interoperability (Java) and breaking the proprietary operating system monopoly (Linux).  Its only when companies started wrapping products and services around them that they really electrified…

Question:

You are simulating your VCO in SpectreRF. 

You ran your PSS + Pnoise (noisetype=sources) simulations using the Shooting engine pss+pnoise and plotted the phase noise. You noticed that the SpectreRF phase noise results differ significantly for...

The world is a mixed-signal one, or at least that's what were told.  The concept of "mixed-signal" simulation has been around since my days at Daisy (some 18 years ago).  And yet, the concept still struggles along. 

Some blame the lack of behavioral modeling expertise.  Others, that the concept of bringing together the hardest aspects of custom and standard cell design together in one fell swoop, is just too…

Transaction-Based Acceleration is becoming more and more important as an extension to In-Circuit Emulation and migration path from simulation. It helps to provide performance gain while maintaining the flexibility of simulation-based tools. There are three goals for this environment:

1. Verification acceleration for HVL-based environment

2. Verification acceleration and system verification for hybrid environment combini…

Question:
From spectre -h pnoise. I find the definition for oscillator linewidth:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
" In a phase noise analysis for an oscillator, the line width, which is also known as the corner frequency, is...

While I suspect that many of our customers have used or heard about the CheckSysConf utility, there may be a few that have no idea how it can help them determine potential Cadence software problems before contacting Cadence Customer Support. More important, CheckSysConf provides information on how to resolve OS/patch issues.

CheckSysConf is a tool that verifies whether the machine on which you want to run the Cadence tools…

When people ask you what you do for a living, is your response as clumsy as mine?  "Um, you see, well I uh, work for this company that sells software that helps people design computer chips?" is typically what I say.  I sometimes say "I'm an Applications Engineer for Cadence Design Systems," and leave it at that.  Either way, the reaction seems to be about the same- the person I'm talking to quickly…

At 45nm chip designs, manufacturing and process control becomes increasingly difficult. Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by traditional (deterministic) STA. STA compensates for this variability…

Just finished packing for a quick trip to Southern California to help kickoff a round of "techtorials" on Coverage-Driven Verification (CDV) this coming week.  (Thus, in a real sense I'm going out help see that the goodness of CDV I described in my last post is communicated in a very direct way!)  Specifically, in Cadence-speak, a techtorial is a 1/2 and 1/2 mix of seminar-style technical training from an…

In my 2004 book, Co-Verification of Hardware and Software for ARM SoC Design, I wrote about the concept of a co-verification engineer. It's the very last section of the book. Although a lot of people told me they read the book (and some actually learned something from it), nobody ever contacted me and said they were a co-verification engineer, so I'll ask again in a slightly different way in 2008.

For many years…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various methods for generating schematic plots into the PDF format. Some have purchased tools, others have bundled together free utilities with custom scripts to accomplish the task. Most have not been able to produce the exact desired content, let alone an intelligent PDF plot.

About two years ago, the SPB R&D and Marketing teams developed not…

So let’s consider a practical example of creating test benches and performing measurements, starting with how to characterize a transistor. A couple of questions to consider before starting are:

What parameters do you want to measure?
What types of test benches are required to measure these parameters?

Let’s start by considering how to measure the ft of a transistor, ft is a standard figure of merit used by analog…

In an announcement concurrent with Semicon West 2008, Shocking Technologies has announced their Cadence Connections membership.  Take a look at the announcement and find out more about how Cadence Allegro PCB and Package designers can benefit from Shocking's rules and materials to safeguard their products from electrostatic discharge (ESD) dangers.

http://www.shockingtechnologies.com/pdf/Shocking_Cadence_Press_Release…

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level synthesis product that improves designer productivity up to 10x in creating and re-using system-on-chip IP.  C-to-Silicon Compiler enables engineers to design at a higher level of abstraction and helps automate the analysis of hardware micro-architecture. 

C-to-Silicon Compiler automatically translates and optimizes abstract behavioral…