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Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1, Part 2, and Part 3 of the series to get up to speed (hopefully soon before it becomes too difficult for me to provide links to every previous topic and too difficult for you to catch up).

We will continue to look at the embedded software aspects of the ARM Integrator Virtual Platform. So far we looked…

Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and I'm finally finding a few minutes to comment on the event. I have a soft spot in my heart for this conference; I think that I've presented something in some form at every show but one since it was called Design SuperCon way back in the mid-90s. I agree with Joe that this is not a major conference for advanced verification folks, but I…

As at most companies these days, Cadence is doing what it can to minimize travel expenses wherever possible.  Consequently, whereas my business trips used to always involve an airplane in some way, these days myself and my colleagues fan out by car from our repective offices to visit customers.  Hence, this week I'm on the road -- literally -- driving behind the wheel of my own vehicle to call on a long time…

Nope - I'm not talking about automobile transmissions ...

I'll continue my series on the SPB16.2 new product features in the coming weeks.

I wanted to take a brief break and talk about, or more importantly learn from you, some of the basic techniques you use in constructing PCB library components. While this may appear to be a simple exercise in building parts for design entry, there are many facets to EDA libr…

[Team Specman welcomes the Technical Publications Team to our blog]

Effectively documenting feature rich, constantly evolving products like Specman, Incisive Enterprise Simulator XL (IES-XL), and Enterprise Manager is a challenge to say the least.  This gives rise to a corresponding challenge for end users: finding the info they need as quickly and easily as possible.  To help address both these issues, we on the "Tech Pubs…

John Pierce, Product Marketing Director for Virtuoso Simulation application gives us some words of wisdom when it comes to getting the most from your simulation investment in 2009.

• Spectre ‘Turbo’ Technology,  MMSIM 7.0, provides 5-10x Performance SPICE was announced in April 2008.
• SpectreRF ‘Turbo’ Technology,

Have you found yourself frustrated at the lack of some decent timing constraints?  Perhaps made critical floorplanning and placement decisions only to have them thrown out because someone forgot to mention a tiny detail in the constraints? Often times, the role of timing constraints is marginalized until it's just too late.  

Instead of assuming the constraints are correct, and getting rid of the attitude "That's not…

Has something like the following ever happened to you?

You've placed and optimized a design, and you see what appears to be timing violations that could be fixed with cell changes on the worst path in the design.  Like the path below that has a lot of "X1" strength cells (don't worry, I contrived this case by timing the design prior to running optDesign to exaggerate the point):

If you wanted to…

I mentioned in my last post that I'd been having lots of fun with power switches lately. One thing I learned how to do was to set up a regular pattern for my switch columns. My first stop for learning something new is always the documentation, but there are so many different options to the addPowerSwitch command that I asked one of our experts, Richard Chou, for help. Setting up a pattern is really quite easy!

Here…

[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field Organization]

There is one very easy step that Specman users can take to roughly double the wall clock, run time performance of their testbench.  In a word, "compile"!

That's right: by simply compiling their e testbench, we've seen customers enjoy substantial performance increases, often up to 2x faster than uncompiled runs…

There's an interesting thread on Cool Verification (http://www.coolverification.com/2009/02/dvcon-misfits-unite.html) about the number of papers at DVCon 2009 authored or co-authored by EDA vendors. There seems to be an assumption on the part of some posters that vendor involvement implies marketing presentations. Not necessarily so! I've certainly seen some conference presentations that were nothing more than recycled…

If you were not lucky enough to be atDesignCon this week, and many of us were not!  You might be interested in the streaming interviews posted on line.  Click here for link.

Scroll down the video soundbites in the right hand pane, list to what Brad says is the emerging trend and focus regarding today's advanced node IC's.

Enjoy!!

And the new features list just keeps going on and on - it's terrific!

In the SPB16.2 release, the Allegro System Architect (ASA), and System Connectivity Manager (SCM) products have been enhanced to provide Differential Pair Swapping capabilities that interface with the Allegro PCB Editor product.

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just joining please refer to Part 1 and Part 2 of the series to get up to speed.

Today's topic is debugging. One of the great things about a Virtual Platform is the ease of debugging code running on the platform. In the first 2 segments we demonstrated how to compile the Linux kernel and run it on the ARM Integrator platform. As…

There is an interesting interview with Nebabie Kebebew, Sr. Product Marketing Manager for Virtuoso APS that elaborates on parallelization technology and how it's been used to deliver improved performance in Virtuoso APS. Take a look, click here!

This week the "DesignCon" show is in town (<= 10 minutes from the Cadence campus at the Santa Clara convention center), so I couldn't resist the opportunity to check out some of the speeches and exhibits.  I'm happy to report that my curiosity was rewarded -- here are my notes along with some photos:

* First, full disclosure: Cadence -- both Corporate and Chip Estimate -- have modest 10x10 booths on…

Allow me to direct your attention to a most welcome article in EDA DesignLine written by Gabe Moretti:

Title: [End] EDA bashing
http://www.edadesignline.com/213000305?cid=RSSfeed_EDAdesignline_edadlALL

In a nutshell, the article argues that general, blanket criticism of the EDA industry -- "EDA bashing" -- is unhelpful to say the least.  I couldn't agree more, and I assure you that my concurrence is not motivated…

Team Specman has been doing a great job supplying nifty tech tips and other useful information about using Specman. Recently, they sent us R&D types a request for new topics to cover. I quickly took them up on it and supplied a post about how to interactively debug when using the Specman Co-Verification Link. Joe asked if I would follow up to clarify the differences between CVL and ISX. These two things are slightly…

[Join Team Specman in welcoming guest blogger Jason Andrews.  Jason is a recognized hardware-software co-verification expert (he's written books on the subject!) and a fellow blogger]

One of the long-time features of Specman is "CVL". It stands for "Co-Verification Link", but is somewhat misnamed. CVL connects a host compiled C program to Specman via a network socket. This feature enables e methods…

I wanted to share some experiences I had with SpectreRF-Turbo and Parasitic reduction on a recent large benchmark. The things I learned may be helpful to anyone who wants to get the most out of turbo and parasitic reduction.

Available in MMSIM7.0.1 and...