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Hey folks, if you are coming to the CDNLive conference, we have a lot of great "techtorials" happening on Monday, September 8. This will be a great opportunity to meet with our technical experts on different tools/solutions.  The classes are small so you will be able to ask questions about the technology and explore how you can use it for your own design needs.

Take a look at the CDNLive webpage, under Monday…

Today, I will discuss some alternatives for chip-level verification with designs that have microprocessors in them. Since I started at Axis Systems back in 2001, the number of designs with processors has steadily gone from a few, to some, to most, to nearly all. Not only do most chips have processors, many have more than one.

For those of you interested in the Power space I recently had an article published on the Power Management DesignLine Europe website that talks about the challenges of capturing and communicating expertise and best practices throughout an organization (both large and small).

The article talks about the ideas behind creating a design kit focused on power, and while not directly talking about Cadence Low Power Kit it does…

Shooting Newton (shooting) and harmonic balance (HB) are complementary technologies and used for circuits that exhibit different behaviors.

The shooting Newton algorithm uses an adaptive time step control, which is particularly effective for sharp transitions...

In this demonstration, we'll show how to perform the following actions:

• Resize a hierarchical instance while maintaining its area
• Create a rectilinear cut in a hierarchical instance
• Convert all guides to fences

Question of the Day: Did you learn anything new in this video?  Or did you know these things already?

• Invented in 1971 by EE professor…

It seems the debate over the benefits of better software verification is still alive and well. I just read a blog post by Frank Schirrmeister on Software Developer Attitude and the topic of hardware vs. software methodology. Part of the post brings up the argument that the cost of failure for hardware is very clear. The deadlines are fixed by tape out, and if the device doesn't work it means major schedule slip, lost revenue…

Today, I'm starting what I hope will be a series of screencasts where I demonstrate some things in SoC-Encounter that I think are better shown through a live demo than through written documentation.  We'll start off with a simple but somewhat hidden capability: Making edits to attributes across multiple selected objects all-at-once using the "Apply All" button on the Attribute Editor.

If the embedded…

When simulating oscillators, it is important to choose the correct simulator engine (shooting Newton vs. harmonic balance.)  In general, we suggest that you use the HB (harmonic balance) engine as your first choice.  In addition, there are situations where...

So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!! 

Now I kinda understand that this could be true for chips that go into leadframe packages, but...for example, lets take a complex wireless radio chip design that…

Inspired by JL Gray of the blog "Cool Verification" who stated, in this post:

"I'd much rather see the marketing guys write a separate blog on their experiences marketing a verification library."

Here goes!

The primary challenge with marketing anything is to crisply answer the audience's selfish-but-totally-fair question of, "what's in it for me?"  Elaborating further, this sentiment…

Friday is that last day to get the Early Bird price for the Embedded Systems Conference scheduled for October 28-30 at the Hynes Convention Center in Boston. There are a lot of great sessions on embedded software development including a track on Debugging, Verification, and Test that will be anchored by my presentation on CDV for embedded software.

Hope to see you there!

[ESC-463] Coverage Driven Verification for Embedded…

What do these 4 have in common? CDNLive! 2008 San Jose - September 8 - 11, 2008. This is an outstanding event where we can learn about how companies are using Cadence solutions to expand their design environments. While most customers attend this event to learn all the new and exciting capabilities of SPB solutions through the customer and Cadence papers/presentations, there are a host of valuable events that are available…

I'm happy to report that the Digital Implementation Forums are picking up momentum now that the old cdnusers.org has been retired.  It is great to see old friends and new ones on the new Cadence.com engaging in some really useful discussions.  We had a couple of posts in particular that are frequent points of discussion and I thought I'd highlight one in the blog here this week.

Forum user Vicky writes (http://www…

In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies -- and more than a handful of leading IC companies -- have started programs to try and bring the manufacturing engineers closer to the design engineers.

The good news, for…

With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?"

If you have ever pondered this challenge, or have tried and failed, or tried and suceeded you may be interested in this article in ChipDesign Magazine.

Have a read. I…

Interesting High-Level Synthesis review by Bryon Moyer at IC Design and Verification Journal. If you want to hear more about High-Level Synthesis and see a live demo, sign-up for a system-level design techtorial at CDNLive! Silicon Valley 2008 on Sept. 8 (Track 2 at 9 a.m.).

There is a new nport parameter, dcextrap, available in MMSIM 6.2.1.  The values are constant or unwrap. The default is constant. dcextrap is typically used when the nport s-parameter data file models a system with long delay – and -- the DC point is not...

Today's SPB 16.2 release is significant for the Cadence Allegro and OrCAD families of products, but more importantly, I think it brings a lot of new functionality for PCB designers.

I will be talking about the improvements in this release over a few blog posts in coming days and weeks.

First and foremost, we have added a Constraint Driven PCB Design Flow for build-up designs to accelerate miniaturization.

As you know, customers…

Today I'm taking a few minutes to jot down a few recent observations about the state of concurrent engineering as it relates to hardware and software verification.

Everybody knows that the opportunity exists to improve time-to-market if projects can get more of the hardware and software done in parallel. Practically, this mostly means getting the software done sooner since it's software that is usually last in the integration…

As the leader of the Cadence OVM development team, I was reading Richard Goering's recent article about the Cadence, Mentor, and Synopsys support for the OVM and VMM class libraries, and I wanted to make sure some key technical points were not lost. 

Before I get to that, I have to say I found it interesting that Synopsys does not plan to support OVM as Goering reported, "Bartleson said, however, that Synopsys has no…