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SystemC is the most common language used for modeling transaction level (TLM) behavior of hardware. From the beginning of TLM users have been exploring how to perform functional verification at the fast TLM level, and hopefully reduce functional verification at the RTL level. The timing might have been a bit premature and theoretical, since it's only very recently that the majority of the market has adopted sophisticated…

Hi All,

With the release of the OVM-e library, there are now many new features available for users to take full advantage of.  I would like to discuss one new feature that, when introduced into a users environment, allows for much greater automation and control over a given simulation run.

The e language has had built-in test phases for close to a decade now.  Users of e will be very familiar with the following phase methods…

As promised, here is my photo blog of Day 1 of DVCon, focused on the OVM Multi-Language tutorial and the show floor.  While I've added descriptive captions to the photos, here are some quick takes:

* Adam, Brett, and the others at the OVM Multi-Language tutorial reported that the session was very interactive, with a lot of great Q&A that indicated a clear need for this enhancement to the methodology.

* FAQ: how was…

If you’ve been wondering how to capture high speed memory interface design intent early in your design process and drive that through to final verification, the Allegro PCB team has a number of ways we can help.

First, be sure to attend or watch a recording of the webinar planned for March 11 where we will walk through some of the latest technology built to address high speed memory interface design.  You can register…

More of our customers are using Incisive for transaction level modeling (TLM) and functional virtual prototyping, analyzing design characteristics before committing to RTL architectures. SystemC is the design language of choice for most of these users, because it is an industry standard, and Incisive provides important connections into the RTL verification flow. Similarly important is the employment of an advanced testbench…

Many of the messages published by Gabe Moretti in his recent EETimes article resonate very well with Cadence strategy. 

Specifically:

• Evolving standards are important with SystemC and TLM becoming the center of the ESL world
  • Cadence supports SystemC with its Incisive Enterprise Simulator and C-to-Silicon high-level synthesis
• The need to connect the "ESL" world into the "RTL" world in order to migrate this …

Specmaniacs and other eRM & OVM users,

Today we offically released the eRM 3.0, er, we mean the "OVM e" library as an open source library: Cadence Enhances Verification with Greater Flexibility

As you also may recall, in parallel Cadence has already donated to the IEEE 1647 Working Group all of the remaining language technologies that underpin eRM that didn't make it into the original IEEE 1647-2006 or 1647…

For those of you that will not be able to make it in person:
So you can follow the action at home, when not on duty in the Cadence booth I'll be snapping pictures for a daily DVCon photo blog along the lines of what I did for CDNLive San Jose last September. (Recall my reports from CDNLive days 0, 1, 2, and 3).  I'll also be bringing my video camera (but one thing I'm learning is that editing video takes a lot more…

IES-XL is comprised of IUS, Incisive Verification Kits with Methodology, Specman, and Enterprise Manager in Desktop Mode.

One of very common query from Incisive Simulator users is the need to view the help of all the IES-XL components together, in a same help browser. The good news is that it is very simple to achieve !!! So, I thought of sharing it here.

Viewing the combined help for IES-XL product: As long as…

[Welecome back the Tech Pubs team as guest bloggers]

Sometimes you just need a little help -- fast.  Like right now; or even yesterday.  Here is the UNIX command to get you the online help you need for Specman and Incisive Enterprise Simulator XL (IES-XL) ASAP:

% product-install-dir/tools/cdnshelp/bin/cdnshelp &

If the "tools" directory is in your path, you can also simply enter the command cdnshelp.  However,…

There is a continuous debate about FPGA prototyping vs. emulation. This debate is heating-up with the latest Synopsys acquisitions of FPGA prototyping tools: Synplicity and Chip-It. This debate sometimes reminds me the endless debate between ASIC and FPGA companies. The reality is that there is a market for both. The FPGA prototyping segment addresses mostly validation of smaller designs or a single IP while emulation…

[Please join Team Specman in welcoming the first guest blogger from our user base: Ms. Kaberi Banerjee, a senior design & verification engineer based in Silicon Valley California]

Fellow Specmaniacs (or should I say "specmites" – in alignment with the subject of bugs!), I recently had a very pleasant encounter with the all powerful Specman “when” sub-typing that I would like to share with you. (When subtyping is one…

Part 2 - I/O TIMING: Talking Outside The Box

It wouldn't be a chip or block if it didn't have to talk to something other than itself right?  We could always assume that every input arrives at exactly the same time, and every output has exactly the same amount of external delay.  The downside is you may never realize some of the more complex aspects of the I/O timing without digging a little further. Last time we…

With the SPB16.2 release, a few new FPGA enhancements have been added.

Over here at Cadence we were pondering the same question and started by estimating the world wide verification…

DVCon 2009 promises much news about System level design and verification. With Open SystemC Initiative (OSCI) events such as the SystemC Users Group, and a TLM2 Modeling and Interoperability Tutorial, there's much to learn and contribute at the event.

Cadence will have a booth and one of the demos is titled:

"Virtual Prototyping with Metric Driven Verification and SystemC TLM2"

It will be available from 2-4pm…

This approach not only avoids an expensive library characterization, which only provides estimates of the component delays, but also has the advantage…

Little did I know that when I accepted an innocent looking meeting propsal from my colleagues on the Blog Team I was destined to be the recipient of the quarterly Cadence blogger award today! 

The scene: this "meeting" turned out to have more attendees than I expected, where my colleagues on the blog team arrived with a whole cast of characters behind them -- my management, our internal Communications specialist, and the…