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  • Verification: Constraint Layering - Fine Tuning Your Environment - Part 2

    teamspecman

    In my last post, I talked briefly about constraint layering in which I gave an extremely simple example of how users can layer constraints on an existing base environment to change how that base environment behaves, all without touching the base environment.

    Obviously, we all know that our verification tasks are more complicated than that simple example.  Therefore, in this edition, I want to go over some additional features…

  • Analog/Custom Design: Video Chat with Lead Architect of Virtuoso Accelerated Parallel Simulator

    deana

    Virtuoso Accelerated Parallel Simulator was just released and I asked Ilya Yusim, lead architect for the new simulator and Nebabie Kebebew, product marketing manager, to tell us what is new and different about this simulator. Check out this video to get a better understanding of what this product brings to the table.

     

     

    If the video fails to embed please click here.  You can also take a look at our feature story…

  • Digital Design: Become an Encounter Digital Implementation System Specialist and Win Cool Prizes

    BobD

    Last week, we announced the Encounter Digital Implementation System along with a cool associated campaign to raise awareness of the technological challenges addressed by this new system. Check out this video for more details:

    If the video fails to embed, please click here.

    Links mentioned in this video:

    • Visit the Encounter Digital Implementation Campaign page here
    • Read more about the prizes here
    • Download the offical…

  • Verification: New Technical Blog on e & Specman Technology

    jvh3
    Specmaniacs of the world: rejoice!  Members of Team Specman have just launched their own blog:

    /posts/teamspecman.aspx

    with the focus on (you guessed it), "all e & Specman, all the time".

    The plan is to make this blog *deeply* technical, adding code examples to posts whenever possible, sponsoring guest bloggers from R&D to show what goes on under-the-hood, etc.

    Enjoy!

  • Verification: Constraint layering - Fine Tuning Your Environment - Part 1

    teamspecman
    In today's environment of ever growing complexity and ever shrinking schedules, simplifying verification code reuse and maintenance is a clear necessity.  To that end, this entry is dedicated to the concept of "constraint layering" in e. This concept is incredibly useful in addressing many issues that one faces when trying to reuse code both across projects in time, across projects that share common characteristics…

  • Verification: New e / Specman Workshops Available Now

    teamspecman
    In response to the continual growth in the e/Specman user community, Team Specman has put together 3 new workshops that are included with the Incisive 8.2 SOCV Kit that shipped just last week.  (Plus: to ensure the content stays fresh, the "plan of record" for these workshops is to continually verify them against the latest tool/code releases for the SOCV Kit and/or track Incisive releases for ever more).…

  • Verification: New Blog - All About e & Specman

    teamspecman
    End-users of e, Specman, Incisive Enterprise Simulator (IES), eRM/OVM e, and loyal Specmaniacs in general: have we got the blog for you!

    As part of Cadence's commitment to support IEEE 1647 e, Team Specman is launching this blog to serve up technical tips, tricks, examples, and observations about developments in IEEE 1647 "e" language-related technologies, methodologies, Specman core engines, and the…

  • System, PCB, & Package Design : What's Good About SPB16.2 OrCAD Capture? Many Usability Enhancements!

    Jerry GenPart

    There are enormous usability updates in the SPB16.2 release of OrCAD Capture. From new ways of managing multiple windows to the ability to place wires and parts using a cross hair cursor - all enhancements are designed to increase ease of use. You can read about the highlights below.

     

    Tabbed windows with docking, floating, and MDI child capabilities:  Now it is easier to manage multiple open windows through tabs that show…

  • Analog/Custom Design: What's New With Virtuoso?

    deana

    If you were wondering what's new with Virtuoso you may want to check out the latest webinars we offered this fall. The IC6.1 Virtuoso Platform, proven through silicon, enables you to "mind those gaps" by delivering customer proven productivity, product quality and schedule predictability improvements. 

    To learn about the latest release of the industry's leading and most comprehensive solution for…

  • Verification: Metric Driven System Level Verification

    jasona

    I have the great honor of introducing a wonderful paper on system level verification by Giles Hall. Giles is recognized by all who know him as a verification expert, and was instrumental in the founding of ISX. He worked tirelessly with numerous customers all over Europe and the North America to demonstrate techniques to improve the state of system level verification and explain how the capabilities of ISX could…

  • Verification: VMM Users -- Welcome to the OVM!

    Adam Sherer

    VMM users -- welcome to the OVM!  We've been talking together about the benefits of the OVM -- ecosystem-drive business value and built-in ability to scale the technical solution -- for quite a while.  While thousands of verification engineers are already using it, many of you have said "Yes, I see the value, but what about my VMM legacy?" In the tradition of the OVM, Cadence (see press release here

    …

  • Digital Design: 3 Reasons Why You Will Want to Download Encounter 8.1

    BobD

    Today is a big day in Digital Implementation land here at Cadence.  Looking around http://cadence.com you'll likely see a lot of information about the new Encounter Digital Implementation System.  I wanted to highlight 3 features (out of the many new features) that I think could be useful to the majority of our users *now*.  Check out this video:

    If the video fails to embed, click here.

    To download the Encounter…

  • System, PCB, & Package Design : What's Good About the SPB16.2 Cross Referencer? Active Links in the Schematic!

    Jerry GenPart

    That's right - an often requested feature from several customers has now been implemented in the SPB16.2 release.

    Just a quick "behind the scenes" glimpse of what several Product Team Support AEs provide during each major SPB product release planning. While the Marketing, Technical Marketing, Sales AEs, and R&D help drive the product features guided by customer input and feedback, the SPB Support AEs…

  • Digital Design: Innovate Your Way Out of Recession With the New Encounter!

    RahulD
    It's official! The U.S. economy has been in a recession for the past year.
    And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession.
     
    "I'm sorry it's happening," said US President George W. Bush, referring to the global financial crisis. In fact we are all sorry but we can’t be moping around, can we? As the…

  • Verification: News From the IP '08 Conference

    jvh3

    My colleagues on the Verification IP team have been honored to present at the annual "IP '08" conference this week in Grenoble, France.  Unfortunately for me I'm not able to attend (hence no photo blog or video; sorry), but my colleague Pete Heller in the Verification IP group has offered to relay the following news about this growing event.

    Q. [Joe] What is IP'08?
    A. [Pete] IP'08 is an annual…

  • Digital Design: Demo: Using the Pin Editor in SoC-Encounter

    BobD

    SoC-Encounter has automatic partition pin assignment capabilites.  The tool also allows us to provide guidance on where partition pins should/should not be allowed to go.  However, it is sometimes useful for certain pins to be placed at certain coordinates, layers, and/or order.  When this level of control is needed, the Pin Editor can help automate the task of moving pins to their desired locations.  This demo shows…

  • Verification: Follow-up on Posedge Software Interview

    jasona

    Just a quick follow-up to my previous interview with Henry Von Bank of Posedge Software. Henry informed me that they are offering ISX consulting services for companies that could use some additional resources integrating and deploying ISX. There is a data sheet with more details and contact information.

  • Verification: e Running Inside VCS Anniversary Updates?

    jvh3

    It's been a year since I heard the first solid report about Synopsys supporting the e language (IEEE 1647-2008) natively inside VCS.  (Note a key distinction here: VCS has interfaced with e language and/or Specman-driven testbenches for years -- that's not what I'm referring to.  The issue here is VCS running e code natively like it runs Verilog natively.)  In the past year I have had many more anecdotes…

  • Digital Design: Tapeout!

    Kari

     

    With an early December tapeout looming, I've found myself too busy to write a post this week. But then I thought, "Why not write about tapeout?".  Here are some things I try to do during a project so that those last few weeks before a deadline are as stress-free as possible:

    Run an early DRC as soon as you get all the library data.
    We usually have three phases of a project: preliminary, stable, and…

  • System, PCB, & Package Design : What's Good About Advanced Plating Bar Checks - Check out the SPB16.2 Release and See!

    Jerry GenPart

    New functionality has been added to the SPB16.2 Allegro Advanced Package Designer (APD) suite of tools to support Advanced Plating Bar Checks.

    The plating bar check command has existed inside of the APD and SiP tools for many years. However, as the design of IC packages has continued to evolve, the needs for this command continue to change. As an example, in the past, it was necessary only to check that the balls of the…

  • Verification: Virtualization and Verification With Posedge Software

    jasona

    Posedge Software is a Cadence Verification Alliance Member with skills in two of my favorite areas: virtualization and embedded software verification. Posedge has worked with ISX as far back as 2006. Besides the fact that they are skilled in verification I must also mention that they are from Minnesota, mostly to prove that my home state is not a complete wasteland and other smart people also live here (even though…

  • Verification: Thoughts on AMS Verification Inspired by the DV Club Lunch

    jvh3

    Last week I had the pleasure of attending a DV Club lunch presentation from Dr. Henry Chang of Designers' Guide Consulting on "What the Digital Verification Engineer Needs to Know about Analog Verification".

    The talk was very engaging, where Dr. Chang's comments on the relatively primitive state of analog verification confirmed my observations in talking with customers and Trailblazer partners…

  • System, PCB, & Package Design : What's Good About HDI Via Structures - Check out the SPB16.2 Release and See!

    Jerry GenPart
    New functionality has been added to the SPB16.2 Allegro PCB Editor suite of tools to support micro vias as distinct design elements.

    This introduces a new methodology to add both conventional and HDI via structures. It includes a new ‘working layer’ model and associated via popup GUI designed to automate the sequence of layer transitions using stacked, staggered and inset vias. We'll cover:
    • Add Via Overview…

  • Digital Design: Coming This Friday November 14th: SoC-Encounter Office Hours

    BobD

    I've really been enjoying the discussions in our Digital Implementation Forums.  Thanks to those who have contributed questions and answers, and to you "lurkers" out there as well.  I appreciate you all- this community is nothing without you!

    A couple of you have reached out and sent me private messages when you've not been able to get complete answers to your questions.  That's fine by me- if…

  • Digital Design: How to Change a Net Name

    Kari

     

    This is a question that comes up once every few months or so: "How do I change the name of a net that I routed by hand? Do I have to delete it and route it again?"

    The answer (thankfully) is no. When would you find yourself in this situation? One example is that you hand-routed a complicated analog or power net, and then got a netlist ECO in which the connections didn't change, but the name of the net…
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