Community

One of the longest standing capabilities in SoC-Encounter is its ability to partition a design- the process by which a design is broken up for hierarchical implementation.  I remember seeing "Big Chip? Go Hierarchical!" in marketing material for Silicon Perspective Corporation before I joined the company back in 2001 (Cadence acquired Silicon Perspective later that year), but it wasn't immediately obvious to me how the…

Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper into the topic of combining formal verification with Cadence's planning & management technology to dramatically improve the throughput of proving assertions, and bug hunting in general.  In a phrase, this is a new "productivity flow" which my colleague Bin Ju previewed in her segment on formal verification technology.

If you would…

The SPB16.2 release is now available (actually, it was available on 10/31/08 from the Cadence software downloads site at - http://downloads.cadence.com/).

Over the next several weeks, I'll be writing about key new features available in this SPB16.2 release. I'd like to hear which features that you've been waiting to see are the most important and useful for your design requirements and which features you'd like us to tune…

In his article in Portable Design, John Donovan wrote:

Palladium Dynamic Power Analysis represents a methodology shift for power budgeting of electronic devices with system-level implications. With a focus on productivity improvement, DPA helps to quickly identify the average and peak power consumption of SoC designs running real software in various operational scenarios. Leveraging Palladium III’s built-in memory and…

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the OVM has grown beyond 5000 registrants to more than 5200.  I took the opportunity to ask Sharath a few questions about his interest in the OVM and how he wants it to develop and here's what he had to say.

I have been working in Rambus Chip Technology (I) Pvt Ltd for past 2…

A few months back I blogged that OVM was "Open for Business".  A nice play on words, if I do say so myself, but is there real opportunity now that the door is open?

5200 OVM World participants.  10,000 downloads.  2100 forum posts.  200+ LinkedIn OVM Professionals.  That certainly describes an active community.  But how do we all monetize the OVM?  Yeah, its pretty obvious how Cadence will monetize it, but a few recent…

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath the metric driven verification and OVM umbrellas, was a great success  (Here is the detailed agenda for reference http://www.secure-register.net/flyer.php?id=260). 

I make this claim not just because of the numbers (a 71% sign-up/attendee ratio -- much higher than the typical 50% you can expect in North America), but because this…

I feel that I must respond to the following blog published by Frank Schirrmeister. Virtual prototypes clearly have their value and their place in the SoC design flow (especially as platforms for software development) but they are hardly a substitute for hardware-assisted solutions and you need to find a way to connect them to your implementation and verification flows otherwise what you see may not be what you get.  Let…

This morning before heading to ESC it dawned on me that the park across the street from my hotel was the Boston Public Garden. Maybe it was the swans on the hotel logo, but the ironic thing is that the only way I knew about this park was by reading the book Make Way for Ducklings to my kids. I previously reported that 4 weeks ago we had a new baby girl. During the week following the birth, as my wife was recovering, I took…

Do you wish you could lock specific aspects of a DEHDL design content? Do you need to standardize on color used for parts, wires, text, etc. in a design? Do you wish designers would maintain a standard grid?

Well - all this (and more!) can be accomplished through the project .cpm file directive locking capabilities available since the SPB16.0 release. I'm writing about this since there are still some customers I interact…

I arrived safe and sound at the Embedded Systems Conference in Boston today. It's been a few years since I have attended ESC, but it all came back to me quickly, and is just as I remember it, a lot of small booths with vendors showing small boards doing something (hopefully something interesting and not something small).

The most interesting talk I attended was Virtualization for Embedded and Real-Time Systems. Virtualization…

The question of how to integrate legacy VMM VIP into OVM verification environments is an issue on the minds of many in the verification ecosystem.  Ed Sperling has written a good article on this subject.

For folks who have been tracking progress on the Accellera VIP TSC reflector, or in the meetings directly, it appears that progress is being made.  Of course, that progress is possible in part because the OVM has been available…

Apologies for the shameless promotion, but I can't resist touting an event I'm producing next Tuesday: an "Advanced Verification Techtorial" on the Cadence San Jose campus.  Here is the detailed agenda:
http://www.secure-register.net/flyer.php?id=260 

If you are the Silicon Valley area next Tuesday (10/28), by all means sign-up and come by:
http://www.secure-register.net/cadence.php?product=3

More on techtorials…

 Most of my experience in functional verification prior to my dabbling in FPV was in the area of SystemC/SCV and simulation acceleration. I naturally brought a simulation-mindset to FPV. As a matter of fact, it is possible to go far in FPV by thinking about the verification problem in procedural terms. Instead of writing BFMs and behavioral checkers, you write properties that each model a small portion of the environment…

It is not too late to sign up for the Package Power Integrity webinar that will be presented on 10/23 11:00 PDT.  Click here to register.

This webinar will give you a heads-up on new (SPB 16.2) features in the package / SiP SI tools that can be used to analyze the package power delivery network (PDN).  Attendees will learn the methodology for validating power delivery by analyzing impedance of the PDN. You'll also learn…

Before getting into the details of today's topic I'm happy to report a brand new baby girl was born on October 1 into the Andrews family of Ham Lake, MN. She is our sixth child, and the forth girl to go along with two boys. Currently, I play a lot of golf with my oldest three kids and with the new baby girl I'm assured the three youngest will form my next foursome after the oldest three grow up and leave home…

 If you've been checking out the other blogs here in the Digital Implementation community, you've probably seen mention of the database access mechanism dbGet/dbSet. Back in the SoC-Encounter 6.x days, our very own BobD gave me a quick demo of dbGet. I couldn't wait for 7.1 to come out, so I could start using it. Of course I got busy with customer projects and never quite found the time to play with it and get…

My first post served as a context for this blog. It also telegraphed my intention to set down a few reasons for the initial difficulties faced by long-time simulation users, specifically verification engineers, in applying formal property verification (FPV). Here is my Top-5 list in no particular order.

1. Procedural Versus Declarative Expression Of Intent

Simulation languages like Verilog, SystemC, e and the rest are procedural…

Today's announcement on our expanding Verification IP (VIP) portfolio inspired me to interview my colleague Dave Tokic to elaborate on this news.  Enjoy the video!

So who is Thad McCracken and why should you be interesting in reading this blog entry?  Thad has been a Cadence Core Comp Senior Technical Leader focused on the Encounter Platform for 6 years(essentially a specialized Applications Engineer that bridges the gap between the field and R&D.)  I sometimes refer to him as “The President and CEO of McCracken Labs” because he has been responsible for some very popular innovations…

In my last post, I talked about how OVM is a methodology for building automated e or SystemVerilog testbenches for Metric Driven Verification (MDV).  As it turns out, one of my colleagues, John Nehls from our Verification Core Comp organization, just wrote an article along similar lines, where he goes into a bit more detail, so rather than repeating what he said, I highly recommend reading his article.

As John points out…

Today, a friend sent me a link to an article on embedded.com that talks about my upcoming presentation at the Embedded Systems Boston Conference. I love the title about turning hardware and software design upside down. I guess it's true that this is what I have been doing for some time.

The unique thing about it was that was the first time I could remember where an article appeared in a publication or on the web that…

Yes, I'm asking about chips that will have 1 billion -- that's billion with a "B" -- logic gates (implying they will have ~6 billion transistors).  Last year I only heard of one such chip in the works anywhere, but just this past month in the course of my travels I received word of two more such massive devices on the drawing board.  Furthermore, judging by the careful silence of some members of the "ClubT…

Hi Everyone!

Welcome to my first blog post! My plan for this space is to share with you various tips and tricks in SoC-Encounter as well as new things I learn along the way. I use Encounter every day as part of my job in Cadence Design Services. Knowledge is a two-way street, so I'm hoping that we'll have some good comments revealing how you, the customers, are using Encounter as well. Now, on to business!

My team…