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Latest Blog Posts

  • RF Engineering: Going broadside with electromagnetic modeling of advanced processes

    archive
    archive
    It has caught my attention that designs using fabrication processes such as 65nm, 45nm, 32nm, and smaller, have changed the landscape when it comes to electromagnetic (EM) modeling of components and interconnects.  These designs have to contend with the...
    • 9 Oct 2008
  • System, PCB, & Package Design : What's Good about the new "Class" Scope for Match Groups in Constraint Manager?

    Jerry GenPart
    Jerry GenPart

    In the SPB16.01 release, for the Constraint Manager in DEHDL, the is a new scope of "Class" for Match Groups.

    This new scope will utilize the “Net Class” signal grouping introduced in 16.0, and allow users to mimic the capability of Bus Scope with this new arbitrary grouping. It will operate as Bus Scope does today, i.e. it is limited to ECSets, and is only used during the ECSet mapping process, creating distinct…

    • 8 Oct 2008
  • Verification: System-level design and verification - at the center!

    Ran Avinun
    Ran Avinun

    This year, Cadence increases its focus on system-level design and verification events. During the latest CDNLive San-Jose that was held in September, the guest keynoteCDNLive Guest Speaker - Dr. Jan Rabaey, Distinguished Professor of Electrical Engineering at the University of California, Berkeley, described the challenges and opportunities facing customers and partners in the years ahead.

    System-level design was the center of his talk. According…

    • 7 Oct 2008
  • Verification: Power Aware Design Now at System Level

    Ran Avinun
    Ran Avinun

    Several years ago, I have purchased a cell phone with a 2 years contract from one of the major wireless service providers in the US. The battery lifetime between charges of this phone was terrible - 24 hours. The service provider promised me that there will be a firmware upgrade which will improve the battery charge time. 9 months later, I uploaded new firmware which allowed me to double the time between charges. These kind…

    • 6 Oct 2008
  • Digital Design: Demo: Calling Global Timing Debug for a Single Path

    BobD
    BobD

    Global Timing Debug has been a very popular capability within SoC-Encounter.  Once you start using it, it becomes hard to go back to looking at text reports.  The high level philosophy of Global Timing Debug is to assess not just the worst path in the design- but all of the failing paths to get a feel for the categories of problems which are blocking timing closure.

    That said, I find that Global Timing Debug visualizes a…

    • 3 Oct 2008
  • Analog/Custom Design: Custom IC design, layouts, and productivity

    archive
    archive

    There is a definite challenge in maintaining productivity when it comes to realizing a design.  Anything that helps the layout with increasing productivity does it for me.  All the marketing and management buzz words apply here; design complexity with shrinking time to market.

    For layout designers in the custom and analog/mixed signal arena, who have increasing productivity demands, Virtuoso IC 6.1.3 and the Virtuoso Layout…

    • 3 Oct 2008
  • System, PCB, & Package Design : CDNLive! MVP discusses modeling 6 Gbps Serial Links with IBIS-AMI modeling

    Maxwell86
    Maxwell86
    Congratulations to Donald Telian and his colleagues at Hitachi and IBM on winning the Most Valuable Paper award at CDNLive! in San Jose. Donald takes you through a case study where a 6 gigabit/second Serial Attached SCSI–2 (SAS-2) interface was architected, simulated, and compliance tested using Cadence Allegro PCB SI GXL.  The analysis featured use of algorithmic models that adhere to the IBIS 5.0 AMI modeling interface…
    • 3 Oct 2008
  • Verification: An informal introduction

    archive
    archive

    Formal verification can mean different things depending upon who you speak to. If I were blogging under Logic Design, it would probably indicate a series of loosely correlated opinions and observations on the topic of equivalency checking. However, this happens to be the Functional Verification forum and this blog about model-checking.

    Model-checking: The process of checking whether a given structure is a model of a given…

    • 3 Oct 2008
  • System, PCB, & Package Design : What's Good About Differential Pair Support in PCB Librarian?

    Jerry GenPart
    Jerry GenPart

    You may recall a post I made a couple months ago about What's Good About Differential Pair Support in ASA?

    In order to establish Differential Pair support for Design Entry HDL (DEHDL), the SPB16.01 release included enhancements to PCB Librarian which allow designers to define diff pair pins.

    With the increased signal speeds of complex designs, differential pair signals are becoming more and more prevalent. In order to…

    • 2 Oct 2008
  • System, PCB, & Package Design : CDNLive! - 10 Gbit package design paper available to conference attendees

    Maxwell86
    Maxwell86

    For those of you that attended CDNLive! but may have missed the presentation on multi-gigabit package design by Kevin Roselle of Bayside Design, you can review the slide presentation by using your conference login and then downloading from here.  Bayside is involved in designing many high-end packages and it was a real eye opener to hear about the trials Kevin and his team have been through as they design and debug these…

    • 1 Oct 2008
  • Verification: Report from last week's "ClubT" events; preview of next week

    jvh3
    jvh3

    As promised, here are some photos last week events, with embedded color commentary. NOTE: there are two additional events next week that will be featuring none other than fellow blogger and Cadence Distinguished Engineer Mike Stellfox:

    • Kista, Sweden on Monday October 6
    • Bristol, UK on Wednesday October 8

    Related note for Silicon Valley California residents: Please save the date of Tuesday, October 28 for a Metric-Driven Verification…

    • 1 Oct 2008
  • Digital Design: Interview: CDNLive! People’s Choice Winner Jason Gentry

    BobD
    BobD

    At the recently completed CDNLive! Silicon Valley 2008 user conference, I had a chance to catch a fantastic presentation on the subject of database access within SoC-Encounter by Jason Gentry from Avago Technologies.  If you'll recall, my very first blog entry in this space was on this exact topic, so I was very interested in attending his session.

    Here is an interview I did with Jason at the conference summarizing…

    • 30 Sep 2008
  • Analog/Custom Design: Custom IC design and design environments

    archive
    archive
    Design environments have come quite a long way from the time I began my engineering career.  It is amazing to see how far we have come from stitching together designs as netlists to run rudimentary simulations, to today’s integrated tools with validation required across a plethora of conditions. In those days, I also remember you only needed one engineer per chip.
     
    With today's levels of design complexity, addition…
    • 29 Sep 2008
  • Verification: Users Take Over at CDNLive! 2008

    jasona
    jasona

    This year I did not attend CDNLive! in San Jose. I wasn't presenting anything and was quite busy with other things. The good news was that there were three ISX (Incisive Software Extensions) users making the presentations so I could stay home and keep working on the new stuff for the upcoming 8.2 release.

    Two years ago at CDNLive! 2006, I presented ISX for the first time to the Cadence Verification Community. The p…

    • 25 Sep 2008
  • Analog/Custom Design: Thanks Mr. Colton: Imitation really is the sincerest form of flattery

    NewYorkSteve
    NewYorkSteve

    Recognize the name Charles Caleb Colton? No? He was a British writer who in 1820 coined the phrase, "Imitation is the sincerest form of flattery." His words could not ring more true today. With some amusement, I watched the unveiling of a "new and revolutionary" custom design product on Monday, September 22.

    As I watched, I could not help to see that it had an umistakable familiarity (which was also…

    • 24 Sep 2008
  • Verification: The cell world

    Ran Avinun
    Ran Avinun
    Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One of the keynote speakers at the show was Mr. Mitsuo Saito, Chief Fellow at Toshiba Corporation Semiconductor Company. Mr. Saito-san delivered a presentation about the 20 years battle for the fastest application-specific processors and the future direction of the semiconductor industry in his mind - dreaming "Cell" world.

    Mr. Saito…
    • 24 Sep 2008
  • System, PCB, & Package Design : TSV, mainstream or niche?

    SiPper
    SiPper

    I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization.  I have heard several companies (foundries and some iDM's) talking about pilot projects in this area, but will it really become prolific?  Are the days of die stacks using wirebonding numbered?

    My belief…

    • 24 Sep 2008
  • Analog/Custom Design: Latest Virtuoso news from CDNLive!

    NewYorkSteve
    NewYorkSteve

    Hey Folks, thanks to all of you who participated in CDNLive SV. There was a lot of great information shared by our customers as to their success using teh latest Virtuoso (which by the way has a new version IC6.1.3 out on downloads). 

    Three presentations that I would call your attention to come from our customers Freescale, Texas Instruments and ST Microelectronics. Each found new and interesting ways of using the advanced…

    • 22 Sep 2008
  • Verification: In the EU next week for "ClubT" verification events

    jvh3
    jvh3
    I'll be in the EU next week supporting "ClubT" events focused on advanced verification, with previews of new developments in the "Trailblazer" program. If you are based in the EU and are active in verification in any way, chances are you have already received a direct invitation to one of these events from our EU team.

    In case these events are news to you (and/or the invite email has been buried…
    • 19 Sep 2008
  • System, PCB, & Package Design : CDNLive! 2008 - San Jose: A brief Re-cap

    Jerry GenPart
    Jerry GenPart

    Wow - what a great time I had attending this year's CDNLive! 2008 event in San Jose. You can read the details in my prior posts from last week, but I'll provide a brief re-cap here:

    • By far, the most valuable aspect of attending CDNLive! is networking with customers and Cadence people. I heard this from all customers I spoke with and personally agree. Meeting the many customers I've worked with as an Application…
    • 17 Sep 2008
  • Analog/Custom Design: Video Demo: Spectre Turbo - Fasten your Seatbelts!!

    archive
    archive

    Although Spectre Turbo was released back in April, I hadn't found time to fully tinker with it. As I explored the idea of highlighting it on the community site, I tested it on at least 6 different designs, from VCOs to PLLs, testing both pre and post-layout, and Spectre Turbo chewed right through my sims. It not only drastically shortened my sim times but also maintained spice accuracy and that’s why I absolutely wanted…

    • 17 Sep 2008
  • Verification: Embedded Software Bugging and Debugging

    jasona
    jasona

    In one of my previous posts I introduced an interesting book titled Dreaming in Code. One of the great quotes from the book pertains to today's subject, embedded software debugging. If you don't have the book you can look it up on the book excerpt page of the author's website for the book.

    If you talk with programmers about this, prepare for whiplash. On the one hand, you may hear that things have never looked…

    • 17 Sep 2008
  • Verification: Getting more value from the OVM using Metric-Driven Verification

    mstellfox
    mstellfox

    With all of the momentum around the OVM these days there has been a lot of good discussion about testbench methodology. The OVM provides a great methodology framework for building modular, reusable verification environments, but there is more needed to get the full value of adopting an HVL like SystemVerilog or e.

    I have seen a lot of people adopt an HVL and continue doing directed testing -- that leads to a whole lot…

    • 15 Sep 2008
  • Verification: Verification community comes together to talk tech

    mstellfox
    mstellfox

    I just finished the week at Cadence's CDNLive User Group in San Jose. Over the past few years, it has really become a great technical event for the verification community. In fact, last year out of all the papers presented across the full breadth of Cadence tools and methodologies, Kelly Larson from Analog Devices won the Most Valuable Paper Award for his presentation which explained the benefits of migrating from VMM…

    • 13 Sep 2008
  • Verification: A few thoughts on CDNLive! and OVM 2.0

    tomacadence
    tomacadence

    My colleague Joe Hupcey has been keeping you informed and entertained with information and photos from this week's CDNLive! Silicon Valley event in San Jose. I've attended a fair number of talks and other activities at the show and I have to say that I found it very enjoyable.

    One of my most fundamental job-related beliefs is that you always learn something anytime you talk to any customer about anything. An event…

    • 12 Sep 2008
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