Community

Highlights of Day 3: papers all morning, lunch, then closing remarks. Comments on the day's events are annotated to the pictures posted here: Click.

Hello from CDNLive Silicon Valley 2008!  I've had a great few days out here interacting with users- especially those who have interests that are well aligned with my areas of focus as an Encounter Applications Engineer.  That for me is the biggest benefit of attending conferences like these- the in-depth discussions you get into that follow on from presentations in the sessions.

One of the coolest things I've seen this…

Lively presentation on IBIS-AMI modeling, multi-gigabit package design, 3D field solvers, and advance constraint management have been taking place this week at CDNLive!  If you have missed it, there is still one more day where you can learn about IC-Package co-design and manufactuing aware package design.  If you do miss it, I'll blog later with pointers to these presentations once they are posted.

Hope to see you…

Highlights of Day 2: more great papers (with enough customer papers on OVM fill almost all of verification track 1), a lot of Designer Expo time (expo for breakfast, lunch and dinner in fact), the new System Level roadmap, and poker!  Here is the day in pictures (from a verification guy's perspective -- there is a lot more going on in the other tracks that I'm missing):

http://www.flickr.com/photos/24605532@N08…

From the floor of CDNLive! 2008 - San Jose

Each day continues to show the value that customers and Cadence employees gather through networking with each other - learning about innovative technical solutions developed to enhance how we interact with the Cadence flows, solutions, and products.

From the floor of CDNLive! 2008 - San Jose

Wow! What an exciting, power packed, and full day - and, it's still going!!

Michael Catrambone (Steering Committee Chairman, UT Starcom, Inc.) and Ted Vucurevich (Senior Vice President, Chief Technology Officer Advanced Research & Development) delivered Welcome remarks.

Here's a picture of us gathering for the Welcome addresses and of Ted during his presentation -

Today we announced important new metric-driven verification capabilities in our enterprise verification solution. My video blog post below provides a quick introduction of the motivations and capabilities. Please take a look and feel free to comment below.

Quick report from CDNLive Day 0 (I've labeled it that since this initial day was devoted to techtorials, ahead of the main events and papers tomorrow) First, the promised photos from the day's events are posted here.

* MDV techtorial snapshot: from the segment I saw, there was a lot of Q&A.  This came as no surprise to me since I've seen the presenter, Solution Architect Paul Carzola, teach this material before…

If you are a system validation/verification engineer, an architect, a power engineer or an embedded SW engineer, you should stop-by and visit us at CDNLive. See below some specific information on what you will be able to see in this domain: Hope to see you there.

- Ran

Day 1 - Monday - was very exciting with fully packed agenda including a full day of system design and verification techtorial with demos, customers and partne…

• The Front End Tools (DEHDL, Constraint Manager, PCB Librarian, ASA)
• PCB SI
• Allegro PCB Editor

Here is a question for all the power grid designers out there: Do you see the need to do quick early dynamic rail analysis during floor and power planning stages of our design? With introduction of the Cadence Encounter Power System today, Cadence First Encounter and SoC Encounter users will have access to the Encounter Power System signoff engines during floor or power planning design stages at no additional cost.

This…

Hey folks, if you are coming to the CDNLive conference, we have a lot of great "techtorials" happening on Monday, September 8. This will be a great opportunity to meet with our technical experts on different tools/solutions.  The classes are small so you will be able to ask questions about the technology and explore how you can use it for your own design needs.

Take a look at the CDNLive webpage, under Monday…

Today, I will discuss some alternatives for chip-level verification with designs that have microprocessors in them. Since I started at Axis Systems back in 2001, the number of designs with processors has steadily gone from a few, to some, to most, to nearly all. Not only do most chips have processors, many have more than one.

For those of you interested in the Power space I recently had an article published on the Power Management DesignLine Europe website that talks about the challenges of capturing and communicating expertise and best practices throughout an organization (both large and small).

The article talks about the ideas behind creating a design kit focused on power, and while not directly talking about Cadence Low Power Kit it does…

Shooting Newton (shooting) and harmonic balance (HB) are complementary technologies and used for circuits that exhibit different behaviors.

The shooting Newton algorithm uses an adaptive time step control, which is particularly effective for sharp transitions...

In this demonstration, we'll show how to perform the following actions:

• Resize a hierarchical instance while maintaining its area
• Create a rectilinear cut in a hierarchical instance
• Convert all guides to fences

Question of the Day: Did you learn anything new in this video?  Or did you know these things already?

• Invented in 1971 by EE professor…

It seems the debate over the benefits of better software verification is still alive and well. I just read a blog post by Frank Schirrmeister on Software Developer Attitude and the topic of hardware vs. software methodology. Part of the post brings up the argument that the cost of failure for hardware is very clear. The deadlines are fixed by tape out, and if the device doesn't work it means major schedule slip, lost revenue…

Today, I'm starting what I hope will be a series of screencasts where I demonstrate some things in SoC-Encounter that I think are better shown through a live demo than through written documentation.  We'll start off with a simple but somewhat hidden capability: Making edits to attributes across multiple selected objects all-at-once using the "Apply All" button on the Attribute Editor.

If the embedded…

When simulating oscillators, it is important to choose the correct simulator engine (shooting Newton vs. harmonic balance.)  In general, we suggest that you use the HB (harmonic balance) engine as your first choice.  In addition, there are situations where...

So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will go into!! 

Now I kinda understand that this could be true for chips that go into leadframe packages, but...for example, lets take a complex wireless radio chip design that…