• Analog/Custom Design Blogs

    Never miss a story from Analog/Custom Design. Subscribe for in-depth analysis and articles.

    Subscribe by email
  • More
  • Cancel
Featured

Virtuoso Studio IC25.1 ISR2 Now Available

Virtuoso Studio IC25.1 ISR2 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Spectre 25.1 Release Now Available

The SPECTRE 25.1 release is now available for download at Cadence Downloads. For…

SpectreReleaseTeam
• 1 min read
featured , Spectre FMC Analysis , Spectre RF , Spectre Photonics , Spectre AMS Designer

Accelerating RFIC EM Analysis with EMX Planar 3D Solver in Virtuoso HI Platform

In modern IC design, especially with the rise of heterogeneous integration, electromagnetic…

Pratul Nijhawan
• 6 min read
blended , blended training , featured , Virtuoso Studio , Virtuoso System Design Environment
Analog/Custom Design
Latest blogs

Spectre Tech Tips: Spectre Assert and Design Check Overview

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use…

• 5 min read
spectre aps , Circuit simulation , asserts , Spectre , SOA Checks , Design Checks

Virtuoso Video Diary: What Makes EM/IR Analysis A Significant Sign-Off Step?

This blog describes the EM and IR analyses in Virtuoso ADE as a design sign-off step…

• 3 min read
ADE Explorer , EM/IR , Power Integrity , IC layout , ADE , Virtuoso Analog Design Environment , Virtuoso Video Diary , sign-off , Custom IC Design , Custom IC , IC design , EMIR

Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available

The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download…

• 3 min read
ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , ADE , Virtuoso Analog Design Environment , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Virtuosity: Maestro Plotting Templates

Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any…

• 3 min read
ICADVM18.1 , ADE Explorer , ViVA , plotting templates , maestro plotting templates , Custom IC Design , IC6.1.8 , ADE Assembler

Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with…

• 2 min read
VCD , Analog Design Environment , ICADVM18.1 , analog , ViVA , Virtuosity , analog stimuli , IC6.1.8 , vector

Virtuosity: Identifying Those Traces

With the ever-increasing number of simulations required to be run these days, the…

• 3 min read
Explorer , plotting , ADE XL , Virtuoso , Analog Design Environment , ViVA , ADE-XL , Virtuosity , Assembler

Spectre Tech Tips: Device Aging? Yes, even Silicon wears out

While most of us would like our electronic gadgets to last forever, the reality is…

• 3 min read
Stress Analysis , TDDB , PBTI , native reliability analysis , Spectre , reliability analysis , HCI , NBTI , reliability

Virtuosity: New Flexible Subwindows

Plots in Cadence Virtuoso Visualization and Analysis can be plotted in a window or…

• 3 min read
ICADVM18.1 , subwindows , waveforms , Virtuoso Analog Design Environment , ViVA , Virtuosity , plotting templates , Custom IC Design , IC6.1.8

Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods

Analog and Mixed-signal (AMS) designs are increasingly using active power management…

• 2 min read
AMS , Virtuoso Schematic Editor , Low Power , virtuoso power manager , Virtuoso-AMS , mixed signal design , mixed signal solution , Virtuoso , low-power design , mixed signal , mixed-signal verification

Virtuosity: A Smart Extracted View

The Cadence Quantus Smart View is the next generation of the Extracted View in the…

• 4 min read
Smart View , PAD , ICADVM18.1 , ADE Explorer , Virtuoso , Virtuosity , Quantus , IC6.1.8 , parasitics , ADE Assembler , Virtuoso Layout Suite XL

Virtuosity: In-design Electromigration Analysis - An efficient way to make layouts…

Shrinking size of ICs with highly complex layouts containing billions of transistors…

• 4 min read
electromigration , ICADV12.3 , ICADVM18.1 , EM/IR , Layout Suite , IC6.1.7 , EM , electrically-aware design , IR drop , IC6.1.8

Break the Wall! Merging Circuit Design Flow and Layout Design Flow for FinFET De…

How can we overcome design challenges with FinFET architecture? Mr. Kazuhiro Oda…

• 4 min read
Analog Design Environment , Virtuoso New Design Platform , Physical placement and layout , Advanced Node , Virtuoso , Custom IC Design

Virtuosity: Virtuoso ADE Verifier in IC6.1.8 and ICADVM18.1 – Better, Faster, Further…

Cutting-edge innovation … Top-down planning … Reliable and formalized verification…

• 3 min read
verifier , PVT , ICADVM18.1 , custom/analog , Formalized Verification , Analog Simulation , ADE , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , space , Custom IC Design , ADE Verifier , IC6.1.8 , ADE Assembler , verification

Virtuoso IC6.1.8 ISR1 and ICADVM18.1 ISR1 Now Available

The IC6.1.8 ISR1 and ICADVM18.1 ISR1 production releases are now available for download…

• 2 min read
Analog Design Environment , ICADVM18.1 , ADE Explorer , Virtuoso Space-based Router , ADE , Layout , Virtuoso , cadenceblogs , IC Release Blog , New in EDA , Virtuoso: The Next Overture , Custom IC Design , Virtuoso Layout Suite , Custom IC , IC6.1.8

Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

An important requirement for project sign-off is to ensure that all the design simulations…

• 2 min read
verifier , PVT , coverage , Analog Coverage , Analog Simulation , Virtuoso Analog Design Environment , space , Custom IC Design , Assembler , verification

Virtuosity: Introducing the Pin Tool

The Pin Tool follows an object-based approach to working with pins by consolidating…

• 2 min read

Spectre Tech Tips: Optimizing Spectre APS Performance

This blog discusses how to optimize the Spectre APS performance for analog and mixed…

• 14 min read
spectre aps , Circuit simulation , ADE Explorer , simulation performance , Simulation Accuracy , Spectre XPS MS , ADE , Spectre Tech Tips , Spectre

Virtuosity: What's New in Run Plan – Part III

After two interesting blogs by Yagya Mishra that explained the most popular features…

• 3 min read
Analog Design Environment , ICADVM18.1 , Rapid Adoption Kit , ADE , worst case corners , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , Run Plan , Custom IC Design , RAKs , IC6.1.8 , ADE Assembler

Accurate Pin-to-Pin Resistance Modeling for Wide, Slotted Metal Structures Using…

In Analog/RF layouts, designers frequently use slotted metal structures. Such slotting…

• 3 min read
Extraction , Quantus

Virtuosity: Saving Time, Effort, and Money with Express Pcells

Use the Express Pcell feature and see for yourself how you can save time, effort…

• 3 min read
Advanced Node , Express Pcell , pcell , Virtuoso , Virtuosity , Layout design , Custom IC Design , Virtuoso Layout Suite , Parameterized Cell , Custom IC , Layout Editing

Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download…

• 2 min read
Virtuoso ICADV12.3 , Analog Design Environment , ICADV12.3 , Routing , IC 6.1 , Mixed-Signal , Virtuoso , Schematic Editor , IC6.1.7 , Virtuoso IC6.1.7 , Virtuoso Layout Suite , ADE Assembler

Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing…

• 7 min read
spectre aps , Spectre EMIR , Virtuoso ADE , Spectre , EMIR , Voltus-Fi XL

Virtuosity: Doing Placement in a Row-Based Environment

At advanced nodes, Virtuoso provides the capability of defining row templates and…

• 5 min read
ICADVM18.1 , Advanced Node , Virtuoso Placer , Virtuoso Layout Suite , Custom IC , Row-Based Placement

Virtuosity: What Did I Miss in Virtuoso Visualization and Analysis and ADE during…

Maybe you've been stuck on a project that used an older version of Virtuoso, maybe…

• 7 min read
ICADV12.3 , ADE Explorer , Virtuoso , ViVA , IC6.1.7 , Custom IC Design , ADE Assembler

Virtuosity: Designing a Row-Based Layout Methodology – Why does this Make Sense at…

At advanced nodes, the complexity and volume of design rules have been growing exponentially…

• 5 min read
ICADVM18.1 , Advanced Node , Virtuoso Placer , Virtuoso , Virtuosity , Custom IC Design , Virtuoso Layout Suite , Row-Based Placement

Virtuosity:"What's In a Name?"

It discusses the benefits of introducing tooltips in the Simulator Options and Analysis…

• 2 min read
ADE Explorer , options , Analysis Options , Choose Analysis , Analysis , ADE , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design , Options form , ADE Assembler

Virtuoso: The Next Overture – Concurrent Layout – a New Methodology for Team Des…

Any task when divided among multiple people gets done quickly... right? What if we…

• 4 min read
Chip finishing , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Layout , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

Virtuosity: Is the Coloring Data Compliant with the MPT Flow?

In advanced node designs, to help you create designs that are compliant with the…

• 2 min read
Advanced Node , Multiple Patterning Technology , Virtuoso , Coloring Engine , Custom IC , Layout Editing
Blog - Title