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  • SpectreReleaseTeam
    SPECTRE 20.1 Release Now Available
    By SpectreReleaseTeam | 2 Oct 2020
    The SPECTRE 20.1 release is now available.
    0 Comments
    Tags:
    spectre aps | Spectre MS | Distributed HB | Spectre | XDP | Spectre X Simulator
  • Stefan Wuensche
    Spectre Tech Tips: Spectre X Update
    By Stefan Wuensche | 29 Sep 2020
    About a year ago, we released Spectre X in the SPECTRE 19.1 base release. Since then, we have released multiple SPECTRE 19.1 ISR releases with incremental Spectre X enhancements. The SPECTRE 20.1 release with major Spectre X enhancements is coming out in early October. In this blog, we'll discuss the Spectre X enhancements that have been delivered in the Spectre 19.1 ISR releases.
    0 Comments
    Tags:
    +preset | LX mode | Distributed HB | XDP | spectre x
  • Parula
    Virtuosity: Usability Enhancements in Simulation Driven Routing
    By Parula | 24 Sep 2020
    Since IC6.1.8 and ICADVM18.1 was released, we have continued our drive to improve the usability of Simulation Driven Routing. Read through this blog to know the key enhancements in this area.
    0 Comments
    Tags:
    Interactive Routing | EAD | ICADVM18.1 | electrically aware design | Virtuoso Layout EXL | Layout Suite | Virtuoso | Virtuosity | simulation driven interactive routing | mixed signal | usability | Custom IC Design | Custom IC
  • Dishika Majumdar
    Virtuosity: What’s New on the Cadence Learning and Support Portal – Part 1
    By Dishika Majumdar | 22 Sep 2020
    Cadence Learning and Support portal has a RAK series that walks you through a sample design flow, illustrating the use of the Custom IC Virtuoso Platform tools at various design stages. Click here to know more.
    0 Comments
    Tags:
    RAK series | Custom IC Design flow | Virtuoso Analog Design Environment | Virtuoso | CIC flow | Custom IC Design | RAKs | Virtuoso Layout Suite | Custom IC
  • Chandrika Durbha
    Virtuoso Video Dairy : Direct Measurements Assistant in Virtuoso Visualization and Analysis XL
    By Chandrika Durbha | 18 Sep 2020
    Ever had to use long expressions just to create simple measurements for plots and waveforms or use markers to measure amplitude, rise, and fall times? That too when these measurements might not even stay in place? If yes, then read on to find out how you can simplify these tasks. From IC6.1.8 ISR13 and ICADVM18.1 ISR13 releases, we have introduced the new Direct Measurements assistant in Virtuoso Visualization...
    0 Comments
    Tags:
    ViVa-XL | Virtuoso Analog Design Environment | Virtuoso | Analog Design Environment | ViVA
  • Arja H
    Virtuosity: Smart View Multi-Process Corners in Virtuoso ADE Assembler and Explorer
    By Arja H | 17 Sep 2020
    Click here to read the latest blog about the updated 'Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit'. This not only explains how to set up and simulate with a Smart View, but also discusses how to simulate with multi-process corners defined in the Smart View.
    0 Comments
    Tags:
    Extraction | Smart View | ICADVM18.1 | ADE Explorer | multi-process corners | Virtuoso Analog Design Environment | Virtuosity | qrc | Custom IC Design | Custom IC | IC6.1.8 | ADE Assembler
  • Arja H
    Virtuosity: Examining Post-Layout Capacitance Using Virtuoso ADE Assembler and ADE Explorer
    By Arja H | 10 Sep 2020
    Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.
    0 Comments
    Tags:
    Analog Design Environment | PAD | ICADVM18.1 | ADE Explorer | Spectre | Virtuosity | Custom IC Design | IC6.1.8 | parasitics
  • danbaldwin
    Virtuoso Meets Maxwell: Thinking Outside the Chip--Advantages of Interoperability Between Best-In-Class IC and IC Packaging Design and Verification Tools
    By danbaldwin | 7 Sep 2020
    Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s...
    0 Comments
    Tags:
    IC Packaging | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso Analog Design Environment | Virtuoso | Spectre | mixed signal | Custom IC Design | Allegro
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire - Episode 5
    By Team ADE Verifier | 27 Aug 2020
    Welcome to the fifth episode of the Veri-Fire series. Check out the new questions and answers that we have for you!
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | custom/analog | Analog Coverage | Analog Simulation | verification plan | analog | ADE | analog verification | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | cadenceblogs | implementations | mixed signal | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | Verifier new feature | custom design technology | ADE Assembler | verification
  • KomalJohar
    Virtuosity: Do Rulers Rule Your Layout Designs?
    By KomalJohar | 25 Aug 2020
    You can now use the segment mode, Auto, while creating the ruler. This feature lets you create multiple rulers in just two clicks.
    0 Comments
    Tags:
    ICADVM18.1 | measurement | ruler | Layout Suite | Virtuoso Layout Suite L | Virtuoso | usability | Virtuoso Layout Suite | Custom IC | IC6.1.8 | Layout Editing
  • deeptig
    Virtuoso Meets Maxwell: Unified Libraries — Making Way For Cross-Platform Flows
    By deeptig | 24 Aug 2020
    Heterogeneous integration of components using different process technologies can appear to be magic! It mitigates the high cost of homogeneous system-on-chip (SOC) integration by allowing designers to combine proven designs, which use older nodes, on substrates by using newer process technologies. Traditional outsourced assembly and test (OSAT) vendors and IC vendors are competing to provide integration methodologies...
    0 Comments
    Tags:
    Technology Independent Layout Pcell | ICADVM18.1 | Unified Library | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso System Design Environment | Virtuoso RF | Cadence SiP Layout | TILP | Custom IC Design | VMM
  • Yagya Mishra
    Virtuosity: What's New in Run Plan - Part IV
    By Yagya Mishra | 20 Aug 2020
    Click here to view our latest blog in the What's New in Run Plan blog series that discusses the enhancements added to the Run Plan assistant across different Virtuoso ADE Assembler IC6.1.8/ICADVM18.1 ISR releases.
    0 Comments
    Tags:
    Virtuoso Analog Design Environment | Virtuoso | Virtuosity | Run Plan | Custom IC Design | Custom IC | IC6.1.8 | Assembler | ADE Assembler
  • Udit Rajput
    Virtuoso Video Diary: The SKILLed Way of Using Plotting Templates
    By Udit Rajput | 20 Aug 2020
    Read through this blog to know more about how to use the maeGetAllPlottingTemplates, maePlotWithPlottingTemplate, and maeSaveImagesUsingPlottingTemplate SKILL functions to work with maestro plotting templates.
    0 Comments
    Tags:
    Cadence blogs | ICADVM18.1 | ADE Explorer | maestro | plotting | Virtuoso Visualization and Analysis XL | Virtuoso Analog Design Environment | Virtuoso | plotting templates | Virtuoso Video Diary | maestro plotting templates | Custom IC Design | SKILL APIs | IC6.1.8 | SKILL | ADE Assembler
  • Virtuoso Release Team
    Virtuoso IC6.1.8 ISR13 and ICADVM18.1 ISR13 Now Available
    By Virtuoso Release Team | 19 Aug 2020
    The IC6.1.8 ISR13 and ICADVM18.1 ISR13 production releases are now available for download.
    0 Comments
    Tags:
    Cadence blogs | ICADVM18.1 | ADE Explorer | EM Solver | Virtuoso Layout EXL | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso | IC Release Blog | Custom IC Design | Virtuoso Layout Suite | Custom IC | ADE Verifier | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire - Episode 4
    By Team ADE Verifier | 13 Aug 2020
    Want to know what's new in this episode of Veri-Fire? Check it out!
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | custom/analog | Analog Coverage | Rapid Adoption Kit | Analog Simulation | analog | ADE | analog verification | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | cadenceblogs | FAQ | implementations | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | Verifier new feature | custom design technology | ADE Assembler | verification
  • skai
    Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution
    By skai | 11 Aug 2020
    While SiP Layout Option is – and continues to be – one of the most complete solutions for package design, the Virtuoso RF Solution gives access to a constantly increasing set of package layout authoring capabilities inside the Virtuoso Layout Suite. Having both IC and package inside the same design platform enables Virtuoso users to do package layout in their preferred design environment. An innovative co-design environment...
    0 Comments
    Tags:
    ICADVM18.1 | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF Solution | Virtuoso RF | Dynamic Shapes | Dynamic Voiding | Custom IC Design
  • Steve PDK Lee
    Virtuoso Meets Maxwell: How Come There is No Mention of Wirebonded ICs?
    By Steve PDK Lee | 2 Aug 2020
    Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time for bringing wirebonds into the spotlight.
    0 Comments
    Tags:
    ICADVM18.1 | Co-Design | Virtuoso System Design Environment | Virtuoso RF | Wirebond | Electromagnetic analysis | Virtuoso | Custom IC Design | Allegro
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire - Episode 3
    By Team ADE Verifier | 30 Jul 2020
    Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | custom/analog | Analog Coverage | ade suite | Analog Simulation | verification plan | custom IC simulation | analog | ADE | analog verification | Mixed-Signal | Virtuoso | Virtuosity | ADE Blog Series | FAQ | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | Verifier new feature | custom design technology | ADE Assembler | verification
  • Udit Rajput
    Virtuoso Video Diary: Enhancements in Reliability Analysis
    By Udit Rajput | 23 Jul 2020
    Read through this blog to know more about the enhancements made to the reliability analysis in Virtuoso ADE Assembler and Virtuoso ADE Explorer over a couple of IC6.1.8 and ICADVM18.1 ISR releases.
    0 Comments
    Tags:
    stress analysis | Cadence blogs | ICADVM18.1 | ADE Explorer | Virtuoso Analog Design Environment | Virtuoso Video Diary | aging | reliability analysis | Custom IC Design | IC6.1.8 | ADE Assembler
  • jgrad
    Virtuoso Meets Maxwell: Cross-Fabric Electromagnetic Extraction - Eliminating the Tedious Work of Merging IC, Package, and Board
    By jgrad | 19 Jul 2020
    With modules coming from multiple platforms, cross-fabric EM analysis becomes an important requirement in Virtuoso RF Solution. The Electromagnetic Solver assistant has an easy solution available for this.
    0 Comments
    Tags:
    Virtuoso ICADVM18.1 | Virtuoso Layout EXL | Virtuoso Meets Maxwell | Virtuoso RF | Electromagnetic analysis | Virtuoso | Custom IC Design | Virtuoso Layout Suite
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire - Episode 2
    By Team ADE Verifier | 16 Jul 2020
    Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!...
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | Analog Coverage | verification plan | analog | ADE | analog verification | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | ADE Blog Series | FAQ | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | Verifier new feature | custom design technology | ADE Assembler | verification
  • KomalJohar
    Virtuosity: Usability Enhancements in the Chop Command of Virtuoso Layout Suite
    By KomalJohar | 10 Jul 2020
    The Chop command in Virtuoso Layout Suite has been enhanced to improve your productivity during interactive wire editing.
    0 Comments
    Tags:
    ICADVM18.1 | Layout Suite | Virtuoso | layout editing chop | usability | Custom IC Design | IC6.1.8
  • Team ADE Verifier
    Virtuosity: In the Line of Veri-Fire - Episode 1
    By Team ADE Verifier | 7 Jul 2020
    Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!...
    0 Comments
    Tags:
    verifier | Analog Design Environment | Cadence blogs | ICADVM18.1 | Analog Coverage | verification plan | analog | ADE | analog verification | Mixed-Signal | Virtuoso Analog Design Environment | Virtuoso | Virtuosity | ADE Blog Series | FAQ | implementations | analog design | Custom IC Design | requirements | Custom IC | ADE Verifier | IC6.1.8 | Assembler | custom design technology | ADE Assembler | verification
  • Dishika Majumdar
    Virtuosity: Good News for our Japanese Readers
    By Dishika Majumdar | 2 Jul 2020
    In this blog, I’m going to share some great news for our Japanese readers. Let's find out what it is…
    0 Comments
    Tags:
    Trunk generation | ICADVM18.1 | AMS Designer | VPR | layout XL | Virtuoso | Japanese blogs | Virtuosity | advanced nodes | ASMD Flex Mode | Virtuoso Layout Suite | Custom IC
  • Virtuoso Release Team
    Virtuoso IC6.1.8 ISR12 and ICADVM18.1 ISR12 Now Available
    By Virtuoso Release Team | 1 Jul 2020
    The IC6.1.8 ISR12 and ICADVM18.1 ISR12 production releases are now available for download.
    0 Comments
    Tags:
    Cadence blogs | ICADVM18.1 | ADE Explorer | EM Solver | Virtuoso RF Solution | IC Release Announcement blog | Virtuoso | IC Release Blog | Virtuoso Layout Suite EXL | Virtuoso Layout Suite | ADE Verifier | IC6.1.8 | ADE Assembler | Virtuoso Layout Suite XL
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