Custom IC Design Blogs

We live in a complex world where it is essential to use and combine tools and platforms as efficiently as possible with all available features. In this blog, we are happy to show you how easy it can be to get best results using the Spectre Simulation Platform and its corresponding options.

The IC6.1.8 ISR15 and ICADVM20.1 ISR15 production releases are now available for download.

Welcome to a post on how to create component and padstack libraries for use in the Virtuoso platform-driven multiple technology flows. This post describes the tasks of a librarian, who must assemble component IP from various sources and create the views and documentation that can be used by designers.

In this blog, I will focus on the key enablers, which are required before the power-aware designs undergo the verification cycle. This is the ultimate test that confirms the robustness and efficiency of a design.

What if you could foresee potential changes in your design and analyze their impact in advance? I’m sure, your life would have been easier, isn’t it? Read on to know more about the what-if or ECO analysis feature in Voltus-Fi-XL.

Today’s blog focuses on in-design checks that offer an easy and convenient way to identify common design issues encountered by the design community while implementing low power schemes. It also helps designers to uncover issues early in the design cycle, avoiding an ECO.

Do you want accurate extraction data for your design, regardless of foundry process and node? Do you want to complete your EMIR setup entirely within the Virtuoso framework? Then explore the new Virtuoso EMIR DSPF flow…

This time I am back with a blog that briefly explains how to set up Virtuoso Power Manager before proceeding with low power verification. To run in-design checks, extract the power intent from a design, or run Conformal Low Power checks, you must first provide inputs that are required by the tool for correct identification of design topology and define the set of rules that apply to those design structures. For example...

Design, Plan, and Analysis - read why it is important to keep these 3 sides of a coin together and how the Virtuoso Design Planning and Analysis tool can help you with this.

Power consumption has always been an overriding concern in electronic design. Consumption relates not only to the power used in the circuitry but also involves monitoring the circuit to prevent overheating. The battery life of any electronic product can be a deciding factor in its success. Designers are continually devising innovative methods to ensure minimal power consumption without impacting the performance of their...

EMIR analysis is one of the more challenging fields of circuit simulation. It requires the power and/or signal net parasitics to be preserved for the later IR drop and EM current analysis. At the same time the EMIR analysis requires SPICE accuracy for properly checking the EM currents against the current limits defined by the foundry. The Cadence transistor level EMIR analysis tool is Voltus-Fi XL which uses the Spectre...

Read through this blog to know more about the usability enhancements made to digital signals in Virtuoso Visualization and Analysis XL.

When you are running the EM analysis for an RF module with a wirebonded IC, an important task is to capture the full coupling between the package and the bond wires. Read this blog to know about a quick and effortless way to do this in Virtuoso RF Solution.

Are you curious to know about the recent developments in Voltus-Fi Custom Power Integrity Solution? Then, check out these five latest features of Voltus-Fi Custom Power Integrity Solution and see how they are working for you.

The shift to heterogeneous integration of module designs implies a transition from PCB-styled flows and methodologies towards IC-styled flows. Cross-fabric design and verification methodologies for multi-die packages have become indispensable parts of any advanced module design flow. Cadence is uniquely positioned to lead and spearhead this transition. To address the challenges of a rapidly increasing market driven by...

Starting from the IC6.1.8/ICADVM18.1 ISR12 releases, Virtuoso ADE Verifier supports Reliability in verification plans. Dive in to know more...

Nowadays, it is more important than ever to use multiple test benches in a single design. Therefore, we are pleased to introduce more tips and tricks for the optimal use of the Virtuoso ADE Product Suite, which comprises of Virtuoso ADE Explorer, Virtuoso ADE Assembler, and Virtuoso ADE Verifier.

The IC6.1.8 ISR14 and ICADVM20.1 production releases are now available for download.

The SPECTRE 20.1 release is now available.

About a year ago, we released Spectre X in the SPECTRE 19.1 base release. Since then, we have released multiple SPECTRE 19.1 ISR releases with incremental Spectre X enhancements. The SPECTRE 20.1 release with major Spectre X enhancements is coming out in early October. In this blog, we'll discuss the Spectre X enhancements that have been delivered in the Spectre 19.1 ISR releases.

Since IC6.1.8 and ICADVM18.1 was released, we have continued our drive to improve the usability of Simulation Driven Routing. Read through this blog to know the key enhancements in this area.

Cadence Learning and Support portal has a RAK series that walks you through a sample design flow, illustrating the use of the Custom IC Virtuoso Platform tools at various design stages. Click here to know more.

Ever had to use long expressions just to create simple measurements for plots and waveforms or use markers to measure amplitude, rise, and fall times? That too when these measurements might not even stay in place? If yes, then read on to find out how you can simplify these tasks. From IC6.1.8 ISR13 and ICADVM18.1 ISR13 releases, we have introduced the new Direct Measurements assistant in Virtuoso Visualization...

Click here to read the latest blog about the updated 'Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit'. This not only explains how to set up and simulate with a Smart View, but also discusses how to simulate with multi-process corners defined in the Smart View.

Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.