Custom IC Design Blogs

The SPECTRE 20.1 release is now available.

About a year ago, we released Spectre X in the SPECTRE 19.1 base release. Since then, we have released multiple SPECTRE 19.1 ISR releases with incremental Spectre X enhancements. The SPECTRE 20.1 release with major Spectre X enhancements is coming out in early October. In this blog, we'll discuss the Spectre X enhancements that have been delivered in the Spectre 19.1 ISR releases.

Since IC6.1.8 and ICADVM18.1 was released, we have continued our drive to improve the usability of Simulation Driven Routing. Read through this blog to know the key enhancements in this area.

Cadence Learning and Support portal has a RAK series that walks you through a sample design flow, illustrating the use of the Custom IC Virtuoso Platform tools at various design stages. Click here to know more.

Ever had to use long expressions just to create simple measurements for plots and waveforms or use markers to measure amplitude, rise, and fall times? That too when these measurements might not even stay in place? If yes, then read on to find out how you can simplify these tasks. From IC6.1.8 ISR13 and ICADVM18.1 ISR13 releases, we have introduced the new Direct Measurements assistant in Virtuoso Visualization...

Click here to read the latest blog about the updated 'Using Quantus Smart View in the Virtuoso Analog Design Environment Rapid Adoption Kit'. This not only explains how to set up and simulate with a Smart View, but also discusses how to simulate with multi-process corners defined in the Smart View.

Post-Layout has become a hot topic recently. This has kept me and several other engineers very busy for the past year or so. One of the new, and exciting post-layout features that we have added to Virtuoso ADE Assembler and Virtuoso ADE Explorer is the ability to view the Spectre Classic Simulator netcap report.

Many of today’s analog, RF, and mixed-signal designs require the integration of multiple ICs across varying substrate technologies to achieve required performance goals. The integration of heterogeneous devices allows designers to achieve results that can’t easily be duplicated using a monolithic IC (SoC) design approach. At the same time, heterogeneous integration introduces a whole new set of challenges for today’s...

Welcome to the fifth episode of the Veri-Fire series. Check out the new questions and answers that we have for you!

You can now use the segment mode, Auto, while creating the ruler. This feature lets you create multiple rulers in just two clicks.

Heterogeneous integration of components using different process technologies can appear to be magic! It mitigates the high cost of homogeneous system-on-chip (SOC) integration by allowing designers to combine proven designs, which use older nodes, on substrates by using newer process technologies. Traditional outsourced assembly and test (OSAT) vendors and IC vendors are competing to provide integration methodologies...

Click here to view our latest blog in the What's New in Run Plan blog series that discusses the enhancements added to the Run Plan assistant across different Virtuoso ADE Assembler IC6.1.8/ICADVM18.1 ISR releases.

Read through this blog to know more about how to use the maeGetAllPlottingTemplates, maePlotWithPlottingTemplate, and maeSaveImagesUsingPlottingTemplate SKILL functions to work with maestro plotting templates.

The IC6.1.8 ISR13 and ICADVM18.1 ISR13 production releases are now available for download.

Want to know what's new in this episode of Veri-Fire? Check it out!

While SiP Layout Option is – and continues to be – one of the most complete solutions for package design, the Virtuoso RF Solution gives access to a constantly increasing set of package layout authoring capabilities inside the Virtuoso Layout Suite. Having both IC and package inside the same design platform enables Virtuoso users to do package layout in their preferred design environment. An innovative co-design environment...

Hello and welcome to Virtuoso Meets Maxwell. If you are a regular reader you might be thinking to yourself, “There’s not a lot about wirebonds in the Virtuoso RF Solution and I’m interested in wirebond support.” That’s a great observation and it’s time for bringing wirebonds into the spotlight.

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!

Read through this blog to know more about the enhancements made to the reliability analysis in Virtuoso ADE Assembler and Virtuoso ADE Explorer over a couple of IC6.1.8 and ICADVM18.1 ISR releases.

With modules coming from multiple platforms, cross-fabric EM analysis becomes an important requirement in Virtuoso RF Solution. The Electromagnetic Solver assistant has an easy solution available for this.

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!...

The Chop command in Virtuoso Layout Suite has been enhanced to improve your productivity during interactive wire editing.

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso ADE Verifier and learn about its various whys and hows. In this series, Dr. Walter Hartong, a Product Engineering Architect at Cadence, will be answering some frequently asked questions on Virtuoso ADE Verifier. Stay tuned for some interesting explanations and solutions!...

In this blog, I’m going to share some great news for our Japanese readers. Let's find out what it is…

The IC6.1.8 ISR12 and ICADVM18.1 ISR12 production releases are now available for download.