Digital Implementation Blogs

This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures missed with traditional IR analysis.

Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high? If the answer is yes, do not worry; Cadence has...

With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.

This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.

Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the timing analysis process easier for you during the synthesis stage. Are you ready to relax? Stop at channel-based Training Bytes on “Useful scripts for Timing Report Analysis” at https://support.cadence.com (Cadence login...

Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the answers.

This blog introduces the Voltus-Celsius Electro-Thermal Analysis RAK that will give you an accelerated start to achieve accurate co-analysis of a power-grid network on a chip-package-PCB system.

A recap of the blogs published in the Library Characterization Tidbits blog series.

With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. This gives great power, performance, and area (PPA) results in complex SoC designs while maintaining quality and design schedule. Do you want to explore...

Are you concerned about the process to integrate third-party DFT insertion during synthesis? Stop worrying!! We have the solution! But: How it is done? What changes are recommended in the script while inserting third-party DFT in Genus? Are there different third-party DFT flows? To answer to all these questions is just a click away in the form of video on “Third-party DFT Insertion Flow in Genus Synthesis...

Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

While using the Cadence Liberate Characterization solution or the Liberate Variety statistical characterization solution, have you encountered a situation where the search for constraints failed to return results within the specified range of arcs and then the related cell was marked as failed? If yes, then do read this blog.

We recently released the Innovus v20.1 software and you might be interested in learning about what's new or changed in the software. Here are some suggestions to get you up to speed: The best place to find all the details of the changes relative to v19.1, is to refer to the What's New document on the Cadence support site . If you want a quick intro to the 20.1 graphical user interface, view this demo that I created...

Read to know about the Liberate AMS command-line flow.

As per Liberty specification, Liberty Variation Format (LVF) modeling is always done at one-sigma. However, did you know that Liberate Variety supports unique settings for characterization and LVF modeling?

A write up on how Liberate MX effectively enables you to characterize only the failed or new arcs.

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.

A recap of the blogs published in the Library Characterization Tidbits blog series.

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT? Is there any scope to improve power consumption of my design? What is the best-case power? Pin-point hot spots in my design? How to recover wasted power? And here is the solution in form of Joules RTL Power Exploration . Joules’ framework for power exploration and power implementation/recovery is stimulus based...

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!! But: How to do it? Is there any specific switch required? What is the flow/script when Joules is...

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences. A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow...

Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI. The webinar answers the following questions: Why did Cadence develop Stylus UI and what is Stylus Common UI? How does someone invoke and use the Stylus Common UI? What are some of the important and useful features of the Stylus Common UI? ...

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning!

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.