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  • Neha Joshi
    iSpatial Flow in Genus: A Modern Approach for Physical Synthesis
    By Neha Joshi | 14 Jul 2020
    With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. This gives great power, performance, and area (PPA) results in complex SoC designs while maintaining quality and design schedule. Do you want to explore...
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    Tags:
    Genus | video | Logic Design | physical implementation
  • Neha Joshi
    Want to Explore Third-Party DFT Insertion Process in Genus?
    By Neha Joshi | 8 Jul 2020
    Are you concerned about the process to integrate third-party DFT insertion during synthesis? Stop worrying!! We have the solution! But: How it is done? What changes are recommended in the script while inserting third-party DFT in Genus? Are there different third-party DFT flows? To answer to all these questions is just a click away in the form of video on “Third-party DFT Insertion Flow in Genus Synthesis...
    0 Comments
    Tags:
    scan | DFT | Logic Design | third-party
  • Priya E Joseph
    Voltus Voice: A New Blog Series to Discover the “Power” Within
    By Priya E Joseph | 29 Jun 2020
    Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.
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    Tags:
    Silicon Signoff and Verification | electromigration | Voltus IC Power Integrity Solution | video | power integrity | training | Voltus | Digital Implementation | Power Sigonff | design closure | IR drop | RAKs | EMIR
  • AbhaRawat
    Library Characterization Tidbits: Did Your Search for Constraints Fail?
    By AbhaRawat | 29 Jun 2020
    While using the Cadence Liberate Characterization solution or the Liberate Variety statistical characterization solution, have you encountered a situation where the search for constraints failed to return results within the specified range of arcs and then the related cell was marked as failed? If yes, then do read this blog.
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    Tags:
    search bound | Liberate Variety | library characterization | glitch metric | Library Characterization Tidbit | Digital Implementation | final state threshold | troubleshooting | Liberate | Constraints | Liberate Characterization Portfolio | glitch tolerance
  • VNelson
    Curious About the Newly Released Innovus Implementation System v20.1?
    By VNelson | 26 Jun 2020
    We recently released the Innovus v20.1 software and you might be interested in learning about what's new or changed in the software. Here are some suggestions to get you up to speed: The best place to find all the details of the changes relative to v19.1, is to refer to the What's New document on the Cadence support site . If you want a quick intro to the 20.1 graphical user interface, view this demo that I created...
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    Tags:
    Digital Implementation | Innovus | Floorplanning and Prototyping
  • Jommy
    Library Characterization Tidbits: Understanding the Liberate AMS Command-Line Flow
    By Jommy | 11 Jun 2020
    Read to know about the Liberate AMS command-line flow.
    0 Comments
    Tags:
    Liberate AMS | Digital Implementation | command line flow | mixed-signal characterization | RAKs
  • AbhaRawat
    Library Characterization Tidbits: Overriding the One-Sigma Rule of Liberty for LVF Modeling
    By AbhaRawat | 28 May 2020
    As per Liberty specification, Liberty Variation Format (LVF) modeling is always done at one-sigma. However, did you know that Liberate Variety supports unique settings for characterization and LVF modeling?
    0 Comments
    Tags:
    tidbits | Liberty Variation Format | LVF modeling | Sigma | sigma factor | variation parameters | Liberate Variety | library characterization | Application Notes | Library Characterization Tidbit | Digital Implementation | Liberate Characterization Portfolio | library validation
  • KamleshSinghDodiya
    Library Characterization Tidbits: Reuse to Recharacterize - Improve Productivity with Liberate MX
    By KamleshSinghDodiya | 15 May 2020
    A write up on how Liberate MX effectively enables you to characterize only the failed or new arcs.
    0 Comments
    Tags:
    memory characterization | incremental run | timing validation | Liberate MX | Digital Implementation | interpolation error | library validation | Rapid Adoption Kits | RAKs
  • AbhaRawat
    Library Characterization Tidbits: Recharacterize What Matters - Save Time!
    By AbhaRawat | 30 Apr 2020
    Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.
    0 Comments
    Tags:
    tidbits | Standard Cell | library characterization | Application Notes | missing arcs | Library Characterization Tidbit | Digital Implementation | ldb | failed arcs | Characterization Solution | Liberate | Liberate Characterization Portfolio
  • Jommy
    Library Characterization Tidbits: Rewind and Replay
    By Jommy | 16 Apr 2020
    A recap of the blogs published in the Library Characterization Tidbits blog series.
    0 Comments
    Tags:
    Liberate AMS | Liberate LV | RAK | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Library Characterization Tidbit | Liberate Characterization Portfolio
  • Neha Joshi
    Joules – Power Exploration Capabilities
    By Neha Joshi | 10 Apr 2020
    Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT? Is there any scope to improve power consumption of my design? What is the best-case power? Pin-point hot spots in my design? How to recover wasted power? And here is the solution in form of Joules RTL Power Exploration . Joules’ framework for power exploration and power implementation/recovery is stimulus based...
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    Tags:
    Low Power | Joules | Logic Design | Power Analysis
  • Neha Joshi
    Exploring Genus-Joules Integration is just a click away!!
    By Neha Joshi | 10 Apr 2020
    Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!! But: How to do it? Is there any specific switch required? What is the flow/script when Joules is...
    0 Comments
    Tags:
    Low Power | Genus | Joules | Logic Design | Power Analysis
  • Neha Joshi
    Genus Synthesis Solution – Introduction to Stylus Common UI
    By Neha Joshi | 9 Apr 2020
    The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences. A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow...
    0 Comments
    Tags:
    Genus | Logic Design | common | stylus
  • VNelson
    Innovus Implementation System: What Is Stylus UI?
    By VNelson | 6 Apr 2020
    Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI. The webinar answers the following questions: Why did Cadence develop Stylus UI and what is Stylus Common UI? How does someone invoke and use the Stylus Common UI? What are some of the important and useful features of the Stylus Common UI? ...
    0 Comments
  • Neha Joshi
    Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution!
    By Neha Joshi | 31 Mar 2020
    Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning!
    0 Comments
    Tags:
    Low Power | Logic Design
  • Jommy
    Library Characterization Tidbits: Validating Libraries Effectively
    By Jommy | 23 Mar 2020
    In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.
    0 Comments
    Tags:
    Liberate LV | timing validation | Digital Implementation | interpolation error | library validation | RAKs
  • AbhaRawat
    Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large Mixed-Signal Blocks
    By AbhaRawat | 6 Mar 2020
    Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.
    0 Comments
    Tags:
    Liberate AMS | video | library generation | pin capacitance | Mixed-Signal | library characterization | shell libraries | Liberate Characterization Portfolio | Liberty | Virtuoso ADE Explorer | Virtuoso ADE Assembler
  • Seena Shankar
    Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio
    By Seena Shankar | 21 Feb 2020
    Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.
    0 Comments
    Tags:
    Liberate Trio Characterization | Unified Flow | Variation Modeling | artificial intelligence | ARM-based Graviton Processors | liberate blog | Amazon Web Services | Multi-PVT | Liberate LV | Liberate Variety | machine learning | aws | PVT corners | Liberate | Liberate Characterization Portfolio | TSMC OPI Ecosystem Forum 2019
  • Jommy
    Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series
    By Jommy | 10 Feb 2020
    As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.
    0 Comments
    Tags:
    Liberate MX validation flow | memory characterization | liberate_mx custom flow | standard custom flow | full custom flow | liberate_mx standard custom flow | compiler characterization | liberate_mx full custom flow | liberate_mx | Liberate MX | Characterization Portfolio
  • Jommy
    Library Characterization Tidbits: A Matrix for Your Reference
    By Jommy | 19 Dec 2019
    When working on multiple tools of the Cadence Liberate Characterization Portfolio, do you tend to get confused about which commands or parameters are supported in a specific tool? Read more...
    0 Comments
    Tags:
    parameter | Liberate AMS | Matrix | liberate blog | Liberate LV | Commands | Liberate Variety | Liberate MX | Liberate | Liberate Characterization Portfolio
  • dpursley
    2019 Annual HLS Survey Results
    By dpursley | 18 Dec 2019
    Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on productivity. Spoiler alert : Users find the HLS flow to be over 2.5x more productive for design and nearly 4x more productive...
    0 Comments
  • Aravind  R
    Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells and IO Cells
    By Aravind R | 5 Dec 2019
    Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.
    0 Comments
    Tags:
    local variation | statistical characterization | AOCV | characterization | liberate trio | mismatch analysis | Liberate Variety | Monte Carlo | standard cells | global variation | lvf | Liberate | Liberate Characterization Portfolio
  • AbhaRawat
    Library Characterization Tidbits: Basics of Standard Cell Characterization and More
    By AbhaRawat | 20 Nov 2019
    Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.
    0 Comments
    Tags:
    tidbits | SPICE netlist | Standard Cell | characterization | Liberty Files | Spectre | Library Characterization Tidbit | Digital Implementation | Characterization Solution | Liberate | Inside-View | Liberate Characterization Portfolio | Rapid Adoption Kits | ECSM | RAKs | CCS | Model Files
  • AbhaRawat
    Library Characterization Tidbits: Reasons to Start Following This New Blog Series
    By AbhaRawat | 7 Nov 2019
    Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.
    0 Comments
    Tags:
    Liberate AMS | videos | Liberate LV | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Liberate | Liberate Characterization Portfolio | RAKs
  • dpursley
    Upcoming Webinar: AI Accelerator Design with Stratus HLS
    By dpursley | 17 Sep 2019
    There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017. Noting the increase in machine learning applications in our user base, we researched how to efficiently move from a TensorFlow model to hardware via Stratus HLS . By July 2018, AI startup Syntiant was talking at DAC about how they went from spec to tapeout in six...
    0 Comments
    Tags:
    High-Level Synthesis | webinars | TensorFlow | machine learning | Stratus | SystemC | HLS
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