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Cadence Modus DFT at International Test Conference 2017

By Rob Knoth | 22 Nov 2017

While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the problems and solutions in academia and the industry....

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automotive | DFT | modus | ATPG | diagnostics | ITC
Functional Correctness—The Forgotten Benefit of HLS

By dpursley | 6 Nov 2017

I like to ask questions, because you learn a lot that way. In fact, I did a survey earlier this year and learned that high-level synthesis users’ experiences are exceeding the non-users’ expectations, and that HLS is being used for a wider variety of design types than even I knew. Recently I asked one of my favorite questions, and got an answer I truly didn’t expect. My favorite question to ask new HLS users: “What...

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High-Level Synthesis | Digital Implementation | HLS | verification
Faster and Smarter

By MeeraC | 5 Oct 2017

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about the state of the EDA industry, especially in the digital and signoff world. It all comes down to the productivity gap between the design diversity and complexity rising faster than the design schedules and other limited resources. This is our fundamental challenge. To overcome those challenges, designers must approach the challenge...

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cdnlive korea | deep learning | CDNLive | machine learning | digital | signoff
2017 Annual HLS Survey Results

By dpursley | 6 Jun 2017

As many of you know, Cadence (more correctly, “I”) recently performed an industry survey about HLS (High Level Synthesis) to get a fuller view of the productivity experiences and expectations from users and non-users alike. With nearly 200 responses, roughly half from HLS users and half not, we got a representative picture of what HLS users, potential users, and even skeptics believe about HLS. So let’s dive in. ...

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High-Level Synthesis | survey | Stratus | HLS
Designing for Low Power… Begin at the Beginning

By dpursley | 1 May 2017

So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL synthesis tools (you certainly can!), but the biggest bang for the buck comes from early design decisions. Next time… start sooner! In fact, experts (not me, real experts ) estimate that optimal architectural (pre...

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Low Power | high level synthesis | power | HLS
“Great” Hardware Design in a Wireless World

By dpursley | 5 Apr 2017

As part three of the “ Making Hardware Design Great Again” series , let’s see how high-level synthesis (HLS) is helping designers create SoCs for WiFi, Bluetooth, and 5G. A common challenge in all three wireless spaces is that their standards are evolving… rapidly. Each new specification, or sub-specification, opens new opportunities. It’s a good opportunity for companies to establish themselves as providers for the...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017 - Part Deux

By dpursley | 28 Feb 2017

In part one of this series, we talked about the role of the hardware designer , specifically comparing the ideal version of the hardware designer with the real-world version. From the emails I received, this is a bittersweet reality for many readers of this blog. Today, we will revisit the life of a hardware designer whose company, like most of the leading semiconductor companies, is using a hardware design paradigm...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017

By dpursley | 22 Feb 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should also make you think. As a hardware designer, is your job great? Is it what you thought you’d be doing when you decided to become a designer? Is it, dare I say, fun? Or, like I hear so many times especially from those designing embedded integrated circuits , are you too bogged down in the muck of cranking out hardware implementations...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Performance, Power, Area. It's All You Need to Know—or Is It?

By BrettCline | 21 Oct 2015

Whether it's in a technical paper, a pundit's article, or a live discussion with a customer, the term PPA—power, performance, and area—is always in the discussion. Of course, PPA is not simply one fixed point. Targets for PPA...

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High-Level Synthesis | PPA | Stratus | SystemC | HLS
Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

By Kari | 21 Aug 2015

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement Optimization . The next step in the flow would be inserting clock trees. Now that we can take advantage of the CCOpt engine to create clock trees, we can also concurrently optimize for timing. But you still have the choice of whether or not to do so. This is a decision that could be design-dependent, and you may want to try both...

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training | ccopt | clock tree synthesis | debugger | Digital Implementation | Innovus
Hot Summer for the High-Level Synthesis Community

By dpursley | 14 Jul 2015

Summer is usually a slow time of the year due to vacations, beautiful weather, and backyard barbeques. But for the HLS community, this summer has started off hot. At the 2015 Design Automation Conference, there was a lot going on with high-level syn...

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High-Level Synthesis | DAC 2015 | SystemC | Brian Bailey | HLS | SystemC Japan 2015
Five-Minute Tutorial: Innovus Placement Optimization

By Kari | 26 Jun 2015

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now I'd like to show you a bit more detail about some of the major steps. One of the new concepts in Innovus is how placement and pre-CTS timing optimization are now combined and interleaved. The GigaPlace placement engine is also new, and you will learn about its features. Click below to play the video (you'll need an active support.cadence...

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GigaPlace | Timing Optimization | Innovus | Placement
Five-Minute Tutorial: The Innovus Standard Flow

By Kari | 8 Jun 2015

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface Tips . Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should start with what's called the Standard Flow. There is a great document on support.cadence.com outlining this flow. I found it very interesting, and I can't wait to try it on my next design. You'll need an active support...

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design flow | Digital Implementation | Innovus | five minute tutorial
Five-Minute Tutorial: Innovus User Interface Tips

By Kari | 2 Jun 2015

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System , our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me assure you that if you are a current Encounter user, you will be able to get around just fine in the Innovus system. A lot of the user interface will look very familiar to you, but there are some important changes and improvements...

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UI | Digital Implementation | Innovus | five minute tutorial
Five Things You Didn’t Know About High-level Synthesis

By dpursley | 24 Apr 2015

Most of you have heard about the promises of high-level synthesis (HLS). Things like improved productivity, quality of results (QoR), and verification all dominate the high-level synthesis collateral, including ours. So here, I’ll mention five ...

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High-Level Synthesis | ECO | Conformal ECO Designer | cadence | Blu Wireless | Forte | Stratus | HLS
High-Level Synthesis: Why Now?

By dpursley | 27 Mar 2015

March 27, 2015 – With a title like “Why Now?”, you might expect this to be a sales blog, a thinly veiled pitch trying to tell you why you should be using high-level synthesis (HLS) today. But, in fact, that is not the point at all. ...

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High-Level Synthesis | EDA | Forte | Stratus | HLS
Five-Minute Tutorial: Inserting Column Power Switches in EDI

By Kari | 20 Feb 2015

Hello my fellow Digital Designers, I'm sorry I haven't been around the blogs much lately. We've had a lot of exciting design work going on that has kept me pretty busy. I hope all of you are having a great 2015 so far. Just a heads up - all links below require a Cadence Online Support account. Our Educational Services team has been busy putting together some short videos called Training Bytes. These are excerpts...

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EDI | Low Power | electronic system design | Cadence Online Support | Encounter Digital Implementation | five minute tutorial | power switch
Five-Minute Tutorial: One More Look at EM Models

By Kari | 20 Oct 2014

Just when you thought you were done setting up EM model files, along came another advanced node with more complicated rules. Sound familiar? I've already posted two Five-Minute Tutorials about EM Model File creation—you can review them here and here —but I need to post one more. In the more recent of the two previous posts, we ended up having to do some hand-editing. Raise your hand if you like to hand-edit important...

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Voltus | Digital Implementation | Power Analysis | EM | five minute tutorial
New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation System

By wally1 | 11 Sep 2014

One question we often hear from experienced physical design engineers migrating to Encounter Digital Implementation System is, "How do I get up to speed on the tool as quickly as possible?" They understand place-and-route (P&R) concepts so they often don't need to attend a full training class over several days. Frequently, they may utilize Rapid Adoption Kits (RAKs), documentation, and other material on Cadence...

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P&R | encounter digital implementation system | place and route | Rapid Adoption Kits | RAKs | physical implementation
Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

By MJ Cad | 14 Apr 2014

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/ Rapid Adoption Kits: Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2 With the help of this RAK (rapid adoption kit) you will learn how to perform static...

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EDI | Encounterer Digital Implementation System | Digital Implementation forums | Tempus | EDI system | Cadence Online Support | digital implementation | Digital Implementation | Encounter Digital Implementation | signoff | timing signoff
Five-Minute Tutorial: Start the New Year with Voltus

By Kari | 9 Jan 2014

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone new who is stopping by to check us out. We're glad you're here and we hope you'll hang out with us for a while! I thought we could start this new year with one of Cadence's newest tools: Voltus IC Power Integrity Solution. You can read all the official details in this news article , but if you're a digital designer like me, you...

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voltagestorm | vstorm | rail analysis | EPS | vector-based | Voltus | IRdrop | power grid view | Power Analysis | EM | vectorless | five minute tutorial | power | RAKs | power grid library
11 Things I Learned by Browsing Cadence Online Support

By MJ Cad | 14 Nov 2013

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available materials at https://support.cadence.com/ . Rapid Adoption Kits (RAKs) - The purpose of RAKs is to demonstrate how users can use Cadence tools in their design flows to improve productivity and to maximize the benefits...

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Digital Implementation forums | How To | Cadence EDI System | power routing | Floorplanning | encounter digital implementation system | beginner | NanoRoute | training | Appnotes | Top Ten | digital implementation | Cadence Encounter Power System | GigaOpt | Digital Implementation | Encounter Digital Implementation | crosstalk | app notes | high performance | Rapid Adoption Kits | encounter power system | OpenAccess | Floorplanning and Prototyping | RAKs | FlipChip
Five-Minute Tutorial: EM Model Files Revisited

By Kari | 18 Sep 2013

Back in January, I posted a Five-Minute Tutorial about creating EM Model files . We'll be referencing this previous post a lot, so check it out quickly right now. That method has worked well for me, but on my most recent project, I hit some snags. As process nodes evolve, the EM models are becoming more complex, and translation scripts are not able to handle all of the cases. So, I had to dig back in and find a new...

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EDI | qrcTechFile | EM Model | ICT | Techgen | iRCX | EPS | digital implementation | EM Model File | Power Analysis | EM | five minute tutorial
Answers to Top 10 Questions on Performing ECOs in EDI System

By wally1 | 17 Apr 2013

Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately based on your design requirements. And adding a tool such as Encounter Conformal ECO Designer or the Encounter Timing System's MMMC Signoff ECO capability can lead to...

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ECO | Cadence EDI System | LEC | encounter digital implementation system | tips and tricks | Synthesis | mmmc
Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis

By Kari | 26 Mar 2013

When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use a perl script to filter out the pwr/gnd bumps and create the voltage source file format. The script would need a bit of editing from project to project, but nothing too complicated...

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EDI | rail analysis | EPS | Five-Minute tutorial | Power Analysis | flip chip | bump

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