Digital Implementation Blogs

With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. This gives great power, performance, and area (PPA) results in complex SoC designs while maintaining quality and design schedule. Do you want to explore...

Are you concerned about the process to integrate third-party DFT insertion during synthesis? Stop worrying!! We have the solution! But: How it is done? What changes are recommended in the script while inserting third-party DFT in Genus? Are there different third-party DFT flows? To answer to all these questions is just a click away in the form of video on “Third-party DFT Insertion Flow in Genus Synthesis...

Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

While using the Cadence Liberate Characterization solution or the Liberate Variety statistical characterization solution, have you encountered a situation where the search for constraints failed to return results within the specified range of arcs and then the related cell was marked as failed? If yes, then do read this blog.

We recently released the Innovus v20.1 software and you might be interested in learning about what's new or changed in the software. Here are some suggestions to get you up to speed: The best place to find all the details of the changes relative to v19.1, is to refer to the What's New document on the Cadence support site . If you want a quick intro to the 20.1 graphical user interface, view this demo that I created...

Read to know about the Liberate AMS command-line flow.

As per Liberty specification, Liberty Variation Format (LVF) modeling is always done at one-sigma. However, did you know that Liberate Variety supports unique settings for characterization and LVF modeling?

A write up on how Liberate MX effectively enables you to characterize only the failed or new arcs.

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.

A recap of the blogs published in the Library Characterization Tidbits blog series.

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT? Is there any scope to improve power consumption of my design? What is the best-case power? Pin-point hot spots in my design? How to recover wasted power? And here is the solution in form of Joules RTL Power Exploration . Joules’ framework for power exploration and power implementation/recovery is stimulus based...

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!! But: How to do it? Is there any specific switch required? What is the flow/script when Joules is...

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences. A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow...

Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI. The webinar answers the following questions: Why did Cadence develop Stylus UI and what is Stylus Common UI? How does someone invoke and use the Stylus Common UI? What are some of the important and useful features of the Stylus Common UI? ...

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning!

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.

When working on multiple tools of the Cadence Liberate Characterization Portfolio, do you tend to get confused about which commands or parameters are supported in a specific tool? Read more...

Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on productivity. Spoiler alert : Users find the HLS flow to be over 2.5x more productive for design and nearly 4x more productive...

Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.

Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017. Noting the increase in machine learning applications in our user base, we researched how to efficiently move from a TensorFlow model to hardware via Stratus HLS . By July 2018, AI startup Syntiant was talking at DAC about how they went from spec to tapeout in six...