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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design

Latest blogs

Training Insight - Gateway to Smarter Diagnostics with Modus DFT Software

In the rapidly evolving landscape of digital semiconductor design and testing, the…

• 2 min read
DFT , Modus DFT , Test , Modus ATPG

Race to First-Pass RTL: Improve PPA Targets Using Stratus HLS

Traditional RTL design methodologies often fall short in the race to deliver faster…

• 5 min read
High-Level Synthesis , online courses , Cadence training , Stratus , SystemC , online training , HLS , cadence learning and support

Enhancing RTL Power Efficiency with xReplay, FlashReplay, and Clock Gating

Innovative Solutions for Power-Efficient RTL Design and Technology As semiconductor…

• 6 min read
digital badge , Low Power , Power-Efficient Design , Joules , training , training bytes , Power Analysis , online training , clock gating , RTL analysis

Power Tradeoffs for Chiplets: What Designers Need to Know

The rise of chiplets in advanced system design presents opportunities as well as…

• 3 min read
chiplets , Voltus IC Power Integrity Solution , Power Integrity

Clock Tree Synthesis (CTS): The Backbone of Physical Design

In the intricate world of digital design, timing is everything. At the heart of this…

• 4 min read
EDI , online courses , HT Algorithme , STA , Cadence Online Support , training , Logic Design , training bytes , clock tree synthesis , Digital Implementation , Innovus , SDC , skew , online training , clock gating

EDA Unplugged: The Behind-The-Scenes Bloopers of Chip Design

Welcome to the binge-worthy series you didn't know you needed—"EDA: Silicon, Security…

• 4 min read
videos , online courses , Electronic Design Automation , training bytes , Semiconductor , online training

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Silicon Signoff and Verification 25.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 25.1 release is now available for download

• 7 min read
ECO , inter-power domain , Silicon Signoff and Verification , power-up analysis , Voltus IC Power Integrity Solution , Tempus , cell electromigration , 3D-IC , Voltus InsightAI , advanced multi-input switching , Power Analysis , 3D-IC Technology , certus , skew , Skew Modeling and Analysis , vectorless

Budgeting Power Like A Pro: Don't Let Your Chip Max Out Its Power Credit Limit

Power planning in chip design is a lot like managing your monthly budget. If you…

• 6 min read
Genus , low-power technique , training , Optimize , online training

Innovus Implementation System 25.1: A Big Leap Forward

The latest Innovus 25.1 major release, packed full of new features and improvements…

• 2 min read
Stylus Common UI , Innovus Implementation System , RTL synthesis

Accelerate Your Design Signoff with Cadence Voltus Training Kit

By Shaleen Bhabu, AE Director ASK and Ronen Stilkol, AE Architect In the rapidly…

• 5 min read
si/pi , fault coverage , voltus training kit , signoff

From Chaos to Clarity: Mastering PBS MiM Flow Without the Land Disputes

Let's face it—when most of us hear "partition," we think of land disputes, family…

• 3 min read
Genus , Cadence Online Support , training , Optimize , Cadence ASK , Synthesis

Elevate Your EDA Skills: Achieve Unmatched PPA with Genus Synthesis Solution

As the electronic design automation (EDA) landscape continues to evolve, the importance…

• 4 min read
training , training bytes , Optimize , Genus Synthesis Solution , Synthesis , online training

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus , Digital Implementation , AI

Semiconductors: Pioneering Extraordinary Growth in the 20th Century

Semiconductors have revolutionized the world, powering everything from smartphones…

• 3 min read
Static timing analysis , online courses , Cadence Online Support , RTL-to-GDSII , Joules , training bytes , Digital Implementation , Innovus , Synthesis , online training , physical implementation , cadence learning and support

Microlearning: The Snackable Knowledge Training Videos

Are you looking to level up your digital design skills—one byte at a time? Ohoo!…

• 5 min read
DFT , RTL2GDSII Flow , online courses , Functional Verification , Gate level simualtion , LEC , STA , Cadence training , training bytes , Digital Implementation , implementation , physical design , Synthesis , RTL design , RTL2GDSII Webinar

Silicon Skylines: Crafting the Future of Electronics

The world of Electronic Design Automation (EDA) is fascinating, where we transform…

• 4 min read
electronic system design , Electronic Design Automation , training , training bytes , Semiconductor , online training

Spaghetti Is Great! Spaghetti Code? Not So Much

Have you ever found yourself in an Italian restaurant, twirling your fork around…

• 3 min read
Digital Implementation , Innovus , tcl

The Power of Less is More! Minimize Power, Maximize Chip's Efficiency!

Optimizing power can be a very convoluted and crucial process. To make design chips…

• 3 min read
Low Power , Genus , training , training bytes , Synthesis , online training

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML

Static Timing Analysis: Cell Delay vs Cell Drive Strength!

Have you ever wondered how a predator succeeds (or) a prey escapes in the jungle…

• 5 min read
featured , Innovus Implementation System , debug , tutorial , STA , cell delay , RTL-to-GDSII , training , Logic Design , training bytes , area , Timing analysis , cell drive strength , signoff , Tempus Timing Signoff Solution , power , online training

Addressing Sequential Elements Optimization in the VLSI Chip Design

With highly advanced technology, the real designs are getting complex, making the…

• 3 min read
digital badge , Genus , online courses , training bytes , Synthesis , online training , Online Support

Need to Reconfigure Your SoC to Meet Functional Safety Standards?

The ISO 26262 standard provides functional safety guidance for semiconductors used…

FormerMember • 1 min read
Automotive , functional safety , midas , ISO 26262

Digital Design Highlights - New Training Releases, Blogs, Videos and Digital Badges…

With another year gone, we look back at our most popular blogs from the year and…

• 4 min read
digital badge , blended training , artificial intelligence , Genus , modus , accelerated learning , cerebrus , RTL-to-GDSII , webinar , training bytes , Digital Implementation , Innovus , certus , cadence learning and support

The Quantum Leap: Equal1 Leverages Cadence Tools for QSoC Design

In today's fast-paced world, the rise of artificial intelligence (AI) is driving…

• 4 min read
quantum , Cryogenic Temperature , Quantum SoC , AI/ML

If You Don't See It, You Might Miss It!

The holiday week is here, and while this is a time for relaxing and re-energizing…

• 3 min read
digital design , DFT , online courses , LEC , RTL-to-GDSII , Digital Design Flow Videos , training bytes , Digital Implementation , implementation , RTL2GDSII , Synthesis , RTL design , Modus ATPG

Voltus Voice: Voltus Takes to the Cloud for Next-Level Scalability

This blog explores how the Voltus solution collaborates with leading cloud providers…

• 3 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Amazon Web Services , EM-IR , microsoft azure , Digital Implementation , Cloud ready , high-performance computing , cloud computing

A Magical World - The Incredible Clock Tree Wizard to Augment Productivity and QoR…

In the era of Artificial Intelligence, front-end designers need a magical key to…

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performance , debug , training , congestion , PPAC , training bytes , clock tree synthesis , area , RTL design , power
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