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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design
Latest blogs

Genus Synthesis Solution – Introduction to Stylus Common UI

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus…

• 1 min read
Genus , Logic Design , common , stylus

Quantus' Substrate Noise Analysis Functionality: RF Spurs Impacting Your Performance…

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence…

• 3 min read
5G , RF , Smart View , SNA , extracted view , Virtuoso , Spectre , qrc , Liberate , signoff , Quantus

Innovus Implementation System: What Is Stylus UI?

Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and…

• less than a min read

Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the…

Optimizing power can be a very convoluted and crucial process. To make design chips…

• 1 min read
Low Power , Logic Design

Library Characterization Tidbits: Validating Libraries Effectively

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for…

• 3 min read
Liberate LV , timing validation , Digital Implementation , interpolation error , library validation , RAKs

Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large…

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization…

• 3 min read
Liberate AMS , video , library generation , pin capacitance , Mixed-Signal , library characterization , shell libraries , Liberate Characterization Portfolio , Liberty , Virtuoso ADE Explorer , Virtuoso ADE Assembler

Are You Struggling to Meet the Timing for Your Design? Stop Worrying!

We know your designs are complex and so is timing analysis. We cannot change the…

• 1 min read

Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton…

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and…

• 3 min read
Liberate Trio Characterization , Unified Flow , Variation Modeling , artificial intelligence , ARM-based Graviton Processors , liberate blog , Amazon Web Services , Multi-PVT , Liberate LV , Liberate Variety , machine learning , aws , PVT corners , Liberate , Liberate Characterization Portfolio , TSMC OPI Ecosystem Forum 2019

Library Characterization Tidbits: Liberate MX for Memory Characterization Video …

As we embark upon our blogging journey again in 2020, in this Library Characterization…

• 3 min read
Liberate MX validation flow , memory characterization , liberate_mx custom flow , standard custom flow , full custom flow , liberate_mx standard custom flow , compiler characterization , liberate_mx full custom flow , liberate_mx , Liberate MX , Characterization Portfolio

Library Characterization Tidbits: A Matrix for Your Reference

When working on multiple tools of the Cadence Liberate Characterization Portfolio…

• 2 min read
parameter , Liberate AMS , Matrix , liberate blog , Liberate LV , Commands , Liberate Variety , Liberate MX , Liberate , Liberate Characterization Portfolio

2019 Annual HLS Survey Results

Each year, we survey the industry to get an idea of the industry’s experiences and…

• 2 min read

Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells…

Let’s read how you can use the Liberate Variety statistical characterization solution…

• 3 min read
local variation , statistical characterization , AOCV , characterization , liberate trio , mismatch analysis , Liberate Variety , Monte Carlo , standard cells , global variation , lvf , Liberate , Liberate Characterization Portfolio

Library Characterization Tidbits: Basics of Standard Cell Characterization and M…

Characterization of standard cell libraries using the Liberate Characterization solution…

• 2 min read
tidbits , SPICE netlist , Standard Cell , characterization , Liberty Files , Spectre , Library Characterization Tidbit , Digital Implementation , Characterization Solution , Liberate , Inside-View , Liberate Characterization Portfolio , Rapid Adoption Kits , ECSM , RAKs , CCS , Model Files

Library Characterization Tidbits: Reasons to Start Following This New Blog Serie…

Library Characterization Tidbits is a blog series aimed at providing insight into…

• 1 min read
Liberate AMS , videos , Liberate LV , Liberate Variety , library characterization , Application Notes , Liberate MX , training bytes , Liberate , Liberate Characterization Portfolio , RAKs

Upcoming Webinar: AI Accelerator Design with Stratus HLS

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine…

• less than a min read
High-Level Synthesis , webinars , TensorFlow , machine learning , Stratus , SystemC , HLS

Safety and Aging in IoT Devices: What We Know Today

How do we achieve highly accurate aging data models for critical circuits in automotive…

• 1 min read
iot devices , DAC 2019 , aging , GlobalFoundries

Now Access Online Support Directly from the Tool Interface

As designs become complex and performance targets increase, time shrinks. Designers…

• 1 min read
Digital Implementation forums , Cadence Online Support , Digital Implementation , Innovus

Exploring AI / Machine Learning Implementations with Stratus HLS

A lot of AI design is done in software and, while much of it will remain there, increasing…

• 4 min read
High-Level Synthesis , TensorFlow , machine learning , Stratus , SystemC , HLS , AI

Need Help with Liberate Commands and Parameters?

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you…

• 1 min read
parameter , Liberate AMS , liberate blog , liberate trio , Liberate LV , Commands , Liberate Variety , Liberate MX , Cadence Help , Digital Implementation , Liberate , Liberty

LIBERATE 19.2 Base Release Now Available

The LIBERATE 19.2 production release is now available for download at Cadence Downloads…

• 2 min read
Liberate AMS , Bolt Job Distribution , Liberate Release Blog , Cadence blogs , characterization , liberate trio , LIBERATE19.2 , Liberate LV , Health Incident Report , Liberate Variety , Liberate MX , Digital Implementation , Ascava Distillation , Liberate , Characterization Portfolio , Liberty , Leakage Power Management

HLS Optimizations You Can't Do By Hand

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable…

• 3 min read
High-Level Synthesis , Stratus , SystemC , HLS

A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss …

• 1 min read
effective resistance , electromigration , clamps , electrostatic discharge , current density , differential voltage , EPS , Voltus , rule file , parallel processing , Innovus , EM , Charged Device Model , massively parallel , bump , ESD

Pattern Technology Applied to Machine Learning-based Hotspot Prediction

I have been working on DFM solutions for (too) many years and the objective hasn…

• 1 min read
pattern analysis , machine learning , silicon learning , signoff , yield , design for manufacturing , DFM

Glitch Noise Analysis and Fixing with Tempus

Every design engineer knows something about glitch but for many the details are a…

• 5 min read
SI , Tempus , STA , delay , noise , glitch , Signal Integrity , crosstalk , signoff , silicon signoff , Sign off , timing

Patterns, a Unified Language between Design and Manufacturing

There will be no design without manufacturing and manufacturing is mainly about patterns…

• 3 min read
pattern analysis , machine learning , yield , design for manufacturing , DFM

2018 Annual HLS Survey Results

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey…

• 2 min read
High-Level Synthesis , 5G , survey , machine learning , Stratus , HLS

ECO with Stratus HLS and the Digital Implementation Flow

For years chip designers have dealt with ECO’s when their source code was written…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , Stratus , HLS

What's in it for Me in Innovus 18.10 Release?

At advanced nodes, there’s always a deep conflict between power, performance, and…

• 1 min read
Digital Implementation forums , Tempus , Release Page , Cadence Online Support , Digital Implementation , Innovus , full flow , blog
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