Featured

Cadence Welcomes VLAB Works

Cadence welcomes VLAB Works, a division of Australian Semiconductor Technology Corporation…

Corporate
• less than a min read
Automotive , featured , Virtual Development Environment , vlab , Protium

Time on Your Side: Launching PSS Perspec Composer

We all agree that time is precious. As PSS ( Portable Stimuli Standard ) models get…

OK202502201742
• 3 min read
featured , Perspec , pss , portable stimulus

Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)

USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in…

Sanjeet Kumar
• less than a min read
Verification IP , eUSB2v2 , featured , Functional Verification , USB
Verification

Latest blogs

Why Do You Need a Simulator-Friendly Debug Tool for UVM Debug?

UVM Testbench Today In 2011, UVM1.0 was introduced to the industry. It has already…

• 6 min read
uvm , debug , Testbench simulation , testbench , VerisiumDebug

Enhancing Network Security with MacSec: Protecting Ethernet Communications

The evolution of technology has led to a rapid increase in data transmission over…

• 2 min read
security , Automotive , Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , System Design and Verification , VIP , Ethernet standards , Automotive Ethernet , encryption , Ethernet , MacSec , Ethernet 400G , verification

Verification of Integrity and Data Encryption (IDE) for CXL Devices

In continuation of our series on IDE blogs, Why IDE Security Technology for PCIe…

• 3 min read

The Crucial Need for Synchronization with Third-Party Systems

In today’s interconnected world, businesses and organizations rely heavily on various…

• 3 min read

Introducing PCIe's Integrity and Data Encryption Feature (IDE)

The Integrity and Data Encryption (IDE) was published in PCIe (Peripheral Component…

• 2 min read
Verification IP , encryption , PCIe , pcie gen6 , IDE

Unraveling the PCIe.6.0 Compliance Feature

In PCI Express (PCIe) devices, there is a need for testing near-worst-case inter…

• 4 min read
Verification IP , VIP , PCIe , feature , PCIe 6.0

Power Up Your Low-Power Verification - A Quick Overview

Handheld devices have evolved immensely over the past decade. Today's smartphones…

• 2 min read
Low Power , Verisium Debug , xcelium , verification

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

Our previous posts in this series covered measuring parameters, switches, and profiling…

• 4 min read
cadence , Xcelium Logic Simulator , xcelium simulator , verification

Best Practices to Achieve the Highest Performance Using Xcelium Logic Simulator …

Xcelium Logic Simulator Profile Analysis Our previous post discussed measuring parameters…

• 4 min read
Xcelium Logic Simulator , profile analysis , xcelium simulator , xcelium , best practices , verification

Understanding PCIe 6.0 Shared Flow Control

As the data rate increases in PCIe 6.0, so do the challenges. If we talk in terms…

• 3 min read
SystemVerilog , Verification IP , PCIe , pcie gen6 , PCIe 6.0 , System Design and Verification , verification

CadenceTECHTALK: Xcelium: The Key to Unlocking Unmatched Mixed-Signal Performanc…

Xcelium mixed-signal simulation is part of Cadence’s verification full flow. The…

• 1 min read
Mixed-Signal , xcelium simulator , xcelium

Best Practices to Achieve the Highest Performance Using Cadence Xcelium Logic Simulator…

In a landscape characterized by increasingly intricate designs and rapidly diminishing…

• 5 min read
Xcelium Logic Simulator , Multi-Core , best practices , verification

Accelerate Design Debugging Using Verisium Debug

Verisium Debug is an advanced debugging tool that helps engineers explore, analyze…

• 1 min read
Verification IP , Verisium Debug , verification

Introduction of Precoding in PCIe 6.0

What Is Precoding in PCIe? With higher speed introduced from PCIe 5.0, high 32…

• 4 min read
Functional Verification , VIP , pcie gen6

Training Insights: Bridging the Skill-Gap with the New Cadence Training Digital IC…

The world is reeling towards AI/ML newer planes, and our EDA world is adding these…

• 2 min read
Functional Verification , System Design and Verification , Coverage-Driven Verification , place and route , digital flow , RTL2GDSII , Synthesis , digital_implementation

Coverage Closure – A Progression Instead of Just a Destination

The testing and verification of a complex hardware or software system, such as modern…

• 2 min read
ml , coverage , bugs , simulation

Exploring World of Flash Memory: Serial, Dual, Quad, and Octal Interface

Overview In the world of digital data storage, flash memory has become an indispensable…

• 3 min read
Verification IP , DATA Storage , flash , serial flash , VIP , Memory Model Portfolio , nor flash , OSPI

Training Insights – A New Free Online Course on the Protium System for Beginner and…

The Cadence Protium System is used for prototyping. It is a hardware platform that…

• 2 min read
digital badge , online_training , protium x2 , Protium , blended_training , training bytes , live

Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus…

The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon…

• 5 min read
Perspec , post-silicon , ATE , pss , portable stimulus , verification

Low-Power IC Design: What Is Required for Verification and Debug?

Low-Power Design Techniques Are Needed In today’s world, energy saving is a hot topic…

• 6 min read
Low Power , debug , Functional Verification , UPF , VerisiumDebug

How to Maximize Productivity and Lower Cost for Enterprise Prototyping

Semiconductor chips are often produced as application-specific integrated circuits…

• 6 min read

Streamlining Your Verification Environment with Xcelium ML

When it comes to projects that involve cover groups and properties, and tests that…

• 1 min read
coverage , xcelium ml , xcelium apps

Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core

The growing design complexity of today’s system on chips can result in long hours…

• 3 min read
DFT , Lightelligence , Multi-Core , xcelium , verification

Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and Python…

The Verisium Debug platform is optimized for scalability, supporting debugging of…

• 1 min read
Verification planning and management , training , webinar , Verisium Debug

Understanding UCIe Design Verification Topologies

UCIe or Universal Chiplet Interconnect Express is the fastest growing chiplet interconnect…

• 3 min read
ucie , Verification IP , chiplet , VIP , die

Accelerating Your Overall HW/SW Verification and Validation Productivity Using Dynamic…

With the increasing complexity of system-on-chip (SoC), the associated software stack…

• 8 min read
Analog Devices. ADI , software verification , validation , protium x2 , palladium z2 , Accelerate , productivity , Hardware/software co-verification , verification

Verisium AI-Driven Verification Platform Improves Debug Productivity by 6X at Re…

With the surge in usage requirements and increasing customer demands, hardware design…

• 3 min read
featured , coverage , throughput , machine learning , Regression , simulation , verification

Training Insights – Webinar –: Solve Tricky SVA Problems with Jasper Visualize and…

Are you experienced in using SVA? It’s been around for a long time, and it’s tempting…

• 2 min read
digital badge , online , Visualize , Jasper , training , webinar , SVA , app , verification
Blog - Title