Cadence Community

Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

By Manoj Chacko | 11 Apr 2017

This morning we announced our next-generation Pegasus Verification System , the biggest breakthrough in SoC physical verification in more than 20 years. Pegasus is architected from the ground up to be a massively parallel, cloud-ready physical verification signoff solution. The groundbreaking technology delivers up to 10X improved design rule check (DRC) performance on hundreds of CPUs while also reducing turnaround time...

0 Comments

TAGS:

Physical verification | CDNLive | pegasus | DRC | design rule check | silicon signoff
Have DRC Tools Run Out of Steam? – Part 2

By Manoj Chacko | 31 Mar 2017

We are continuing the physical verification blog posts with more questions we hear from advanced node customers. Paul McLellan had a nice blog post Dracula, Vampire, Assura, PVS: A Brief History on the history of the tools in physical verification. Christen Decoin posted Have DRC Tools Run Out of Steam? – Part 1 , which outlined DRC market history by the timelines. DRC1.0, which was the single CPU DRC run era, followed...

0 Comments

TAGS:

massively scalable | DRC | multithread | distributed processing
Have DRC Tools Run Out of Steam? – Part 1

By Christen Decoin | 13 Mar 2017

In the EDA history of design rule check (DRC), there have been two distinct eras so far. The first is the era of a single run on--a single CPU that enabled designers to run their DRC on technology nodes ranging from 1um to 0.18um, which we refer to as DRC 1.0. The second is the era of the multi-threaded DRC--runs that were introduced to meet the performance requirements at process technologies ranging from 0.18um to 28nm...

0 Comments

TAGS:

Physical verification | DRC | design rule check

Silicon Signoff Blogs

Cadence Community