Silicon Signoff Blogs

We are excited to share that PegasusTM Verification System Product page is now live on Cadence Online Support site. This page is the one-stop destination where you will get all PegasusTM related information. Here is the glimpse of the page: Let&rsqu...

The SSV 20.1 production release is now available for download.

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence when I visited an acoustic anechoic chamber. I could hear my own heartbeat, vibration of my cells, and the fluids running through my veins. The absence of sound was ...

We know your designs are complex and so is timing analysis. We cannot change the design but we have made the timing analysis process easier for you. Timing closure is one of the most critical components of a digital design. To be able to meet timing ...

How do we achieve highly accurate aging data models for critical circuits in automotive or IoT applications? IoT device aging isn’t well understood yet, since most of it is still so new. How will the software stand up against tomorrow’s t...

I have been working on DFM solutions for (too) many years and the objective hasn’t change: Detect or predict design-process weakpoints also known as hotspots, to limit systematic yield loss in semiconductor manufacturing. Traditional methods, c...

Every design engineer knows something about glitch but for many the details are a little fuzzy, especially since the topic has recently evolved well beyond the original, simple analysis. I will use this posting to sketch a quick overview of the state...

There will be no design without manufacturing and manufacturing is mainly about patterns and patterning. Without proper transfer of the design patterns to silicon, there would be no semiconductor product. So, it’s with no surprise that several ...

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. On Feb. 28 you can hear from AMD and Cadence on “Applying mac...

How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Des...

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” that Jason Cain, Principal Member of the Technical Staff with AMD gave earlier at the SPIE...

These days, DRC rule deck availability for the market tools is not a major issue for customers designing on advanced nodes. All EDA vendors work closely with the foundries to facilitate the enablement. The bigger problem is that customers cannot get ...

This morning we announced our next-generation Pegasus Verification System , the biggest breakthrough in SoC physical verification in more than 20 years. Pegasus is architected from the ground up to be a massively parallel, cloud-ready physical verification...

We are continuing the physical verification blog posts with more questions we hear from advanced node customers. Paul McLellan had a nice blog post Dracula, Vampire, Assura, PVS: A Brief History on the history of the tools in physical verification. Christen...

In the EDA history of design rule check (DRC), there have been two distinct eras so far. The first is the era of a single run on--a single CPU that enabled designers to run their DRC on technology nodes ranging from 1um to 0.18um, which we refer to as...