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Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

By Philippe Hurat | 14 Feb 2018

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. On Feb. 28 you can hear from AMD and Cadence on “Applying mac...

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Get Early Silicon Learning to Accelerate Yield Ramp-up

By Philippe Hurat | 5 Dec 2017

How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Des...

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TAGS:

DNA | pattern analysis | machine learning | silicon learning | yield | test chip | design for manufacturing | DFM
How to Measure and Improve Design Regularity for Better Yield

By Philippe Hurat | 9 Nov 2017

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” that Jason Cain, Principal Member of the Technical Staff with AMD gave earlier at the SPIE...

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TAGS:

pattern analysis | machine learning | analytics | yield | silicon signoff | design for manufacturing | DFM
Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years.

By Manoj Chacko | 11 Sep 2017

These days, DRC rule deck availability for the market tools is not a major issue for customers designing on advanced nodes. All EDA vendors work closely with the foundries to facilitate the enablement. The bigger problem is that customers cannot get ...

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TAGS:

Physical verification | massively scalable | pegasus | DRC | Cloud ready
Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

By Manoj Chacko | 11 Apr 2017

This morning we announced our next-generation Pegasus Verification System , the biggest breakthrough in SoC physical verification in more than 20 years. Pegasus is architected from the ground up to be a massively parallel, cloud-ready physical verification...

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TAGS:

Physical verification | CDNLive | pegasus | DRC | design rule check | silicon signoff
Have DRC Tools Run Out of Steam? – Part 2

By Manoj Chacko | 31 Mar 2017

We are continuing the physical verification blog posts with more questions we hear from advanced node customers. Paul McLellan had a nice blog post Dracula, Vampire, Assura, PVS: A Brief History on the history of the tools in physical verification. Christen...

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TAGS:

massively scalable | DRC | multithread | distributed processing
Have DRC Tools Run Out of Steam? – Part 1

By Christen Decoin | 13 Mar 2017

In the EDA history of design rule check (DRC), there have been two distinct eras so far. The first is the era of a single run on--a single CPU that enabled designers to run their DRC on technology nodes ranging from 1um to 0.18um, which we refer to as...

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TAGS:

Physical verification | DRC | design rule check

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