Cadence Community

SSV 20.1 Base Release Now Available

By SSV Release Team | 15 May 2020

The SSV 20.1 production release is now available for download.

0 Comments

Tags:

Vector Profiler | Signoff ECO | Tempus | Tempus PI | integrated signoff | power integrity | Voltus | Voltus-XP
Quantus' Substrate Noise Analysis Functionality: RF Spurs Impacting Your Performance? Not Anymore!

By Hitendra | 8 Apr 2020

Is there anything called pindrop silence? Oh yes, I experienced the sound of silence when I visited an acoustic anechoic chamber. I could hear my own heartbeat, vibration of my cells, and the fluids running through my veins. The absence of sound was ...

0 Comments

Tags:

5G | RF | Smart View | SNA | extracted view | Virtuoso | Spectre | qrc | Liberate | signoff | Quantus
Are You Struggling to Meet the Timing for Your Design? Stop Worrying!

By MJ Cad | 26 Feb 2020

We know your designs are complex and so is timing analysis. We cannot change the design but we have made the timing analysis process easier for you. Timing closure is one of the most critical components of a digital design. To be able to meet timing ...

0 Comments
Safety and Aging in IoT Devices: What We Know Today

By XTeam | 11 Sep 2019

How do we achieve highly accurate aging data models for critical circuits in automotive or IoT applications? IoT device aging isn’t well understood yet, since most of it is still so new. How will the software stand up against tomorrow’s t...

0 Comments

Tags:

iot devices | DAC 2019 | aging | GlobalFoundries
Pattern Technology Applied to Machine Learning-based Hotspot Prediction

By Philippe Hurat | 20 Feb 2019

I have been working on DFM solutions for (too) many years and the objective hasn’t change: Detect or predict design-process weakpoints also known as hotspots, to limit systematic yield loss in semiconductor manufacturing. Traditional methods, c...

0 Comments

Tags:

pattern analysis | machine learning | silicon learning | signoff | yield | design for manufacturing | DFM
Glitch Noise Analysis and Fixing with Tempus

By Marc Swinnen | 3 Jan 2019

Every design engineer knows something about glitch but for many the details are a little fuzzy, especially since the topic has recently evolved well beyond the original, simple analysis. I will use this posting to sketch a quick overview of the state...

0 Comments

Tags:

SI | Tempus | STA | delay | noise | glitch | signal integrity | crosstalk | signoff | silicon signoff | Sign off | timing
Patterns, a Unified Language between Design and Manufacturing

By Philippe Hurat | 23 Dec 2018

There will be no design without manufacturing and manufacturing is mainly about patterns and patterning. Without proper transfer of the design patterns to silicon, there would be no semiconductor product. So, it’s with no surprise that several ...

0 Comments

Tags:

pattern analysis | machine learning | yield | design for manufacturing | DFM
Wondering How Moving To Advanced Nodes Might Affect Manufacturability And Yield?

By Philippe Hurat | 14 Feb 2018

At the upcoming SPIE Advanced Lithography conference (Feb. 25 – March 1, San Jose, CA) you can hear from experts in the field on how these challenges are being addressed. On Feb. 28 you can hear from AMD and Cadence on “Applying mac...

0 Comments
Get Early Silicon Learning to Accelerate Yield Ramp-up

By Philippe Hurat | 5 Dec 2017

How important is it for your advanced node products to get early silicon learning? How are your test chips compared to real products? Some answers are provided below in short summary from the “Methodology for Analyzing and Quantifying Des...

0 Comments

Tags:

DNA | pattern analysis | machine learning | silicon learning | yield | test chip | design for manufacturing | DFM
How to Measure and Improve Design Regularity for Better Yield

By Philippe Hurat | 9 Nov 2017

The following post is an excerpt of “Methodology for Analyzing and Quantifying Design Style Changes and Complexity using Topological Patterns” that Jason Cain, Principal Member of the Technical Staff with AMD gave earlier at the SPIE...

0 Comments

Tags:

pattern analysis | machine learning | analytics | yield | silicon signoff | design for manufacturing | DFM
Why Pegasus Is the Biggest Breakthrough in SoC Physical Verification in 20 Years.

By Manoj Chacko | 11 Sep 2017

These days, DRC rule deck availability for the market tools is not a major issue for customers designing on advanced nodes. All EDA vendors work closely with the foundries to facilitate the enablement. The bigger problem is that customers cannot get ...

0 Comments

Tags:

Physical verification | massively scalable | pegasus | DRC | Cloud ready
Let Your DRC Fly! Cadence Announces Breakthrough in SoC Physical Verification

By Manoj Chacko | 11 Apr 2017

This morning we announced our next-generation Pegasus Verification System , the biggest breakthrough in SoC physical verification in more than 20 years. Pegasus is architected from the ground up to be a massively parallel, cloud-ready physical verification...

0 Comments

Tags:

Physical verification | CDNLive | pegasus | DRC | design rule check | silicon signoff
Have DRC Tools Run Out of Steam? – Part 2

By Manoj Chacko | 31 Mar 2017

We are continuing the physical verification blog posts with more questions we hear from advanced node customers. Paul McLellan had a nice blog post Dracula, Vampire, Assura, PVS: A Brief History on the history of the tools in physical verification. Christen...

0 Comments

Tags:

massively scalable | DRC | multithread | distributed processing
Have DRC Tools Run Out of Steam? – Part 1

By Christen | 13 Mar 2017

In the EDA history of design rule check (DRC), there have been two distinct eras so far. The first is the era of a single run on--a single CPU that enabled designers to run their DRC on technology nodes ranging from 1um to 0.18um, which we refer to as...

0 Comments

Tags:

Physical verification | DRC | design rule check

Silicon Signoff Blogs