• Discussion

  Layout XL stop layers (again) Locked

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  2 replies
  Latest over 3 years ago
  by tdtg
• Discussion

  Availability of Sensitivity results in Assembler after corner run? Locked

  8304 views
  1 reply
  Latest over 3 years ago
  by Andrew Beckett
• Discussion

  Tip of the Week - How to update the Trace-End Properties in an SPD file

  832 views
  0 replies
  Started over 3 years ago
  by SimTech
• Discussion

  SystemVerilog AMS simulation (ADE) xmelab ERROR, TYCMPAT: port or terminal connection type check failed on instance (expecting datatype compatible with 'packed array' but found 'unpacked array[0:1] of packed array [3:0] of logic' instead) Locked

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  5 replies
  Latest over 3 years ago
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• Discussion

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  2 replies
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• Discussion

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  1 reply
  Latest over 3 years ago
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• Discussion

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  1 reply
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• Discussion

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  1 reply
  Latest over 3 years ago
  by SimbaG
• Not Answered

  Can I design a PCB with different outline at each layer? 0

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  1 reply
  Latest over 3 years ago
  by SOT23
• Answered

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  1 reply
  Latest over 3 years ago
  by BIPal
• Discussion

  dynamic selection totally freezes layout xl when there are many connectivity warnings Locked

  8549 views
  2 replies
  Latest over 3 years ago
  by tdtg
• Discussion

  override maximum FET length in schematic pcell to match layout MOSCAP dimensions Locked

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  2 replies
  Latest over 3 years ago
  by tdtg
• Discussion

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  27991 views
  21 replies
  Latest over 3 years ago
  by Andrew Beckett
• Discussion

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  4 replies
  Latest over 3 years ago
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• Discussion

  connectRules for multiple power domain Locked

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  2 replies
  Latest over 3 years ago
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