• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

×

Welcome to the Community Recognition Program!

The Community Recognition Program is a way for Cadence to recognize community participation. By sharing your real-world expertise and broadening your knowledge, you will earn points and increase your reputation.

We encourage you to give answers as well as seek answers. You’ll both expand your skill set and help others expand theirs, and that expansion will be visible and valuable to the entire community.

So, join in. Start a conversation. Ask a question. Be the reason that a question gets solved. And last but not least, don’t forget to have fun!

learn More

Cadence Community Forums

Connect with Cadence experts and users around the globe to share ideas and best practices

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Take the Website Tour - Watch Now

CDNS Forum Categories

Browse Cadence Community Forums

Show All

OnCloud Platform

AWR Design Environment

Custom IC Design

Custom IC SKILL

PCB Design & IC Packaging (Allegro X)

System Analysis

OrCAD X

Computational Fluid Dynamics

Functional Verification

Digital Implementation

Mixed-Signal Design

Logic Design

Verification IP

RF Design

High-Level Synthesis

Implementation

PCell Designer

Functional Verification Shared Code

Hardware/Software Co-Development, Verification and Integration

RAVEL DRC Programming for IC Packaging and PCB

Community Super User Program

Want to know more? Check out this section!

Participate Now
CDNS Feature Content

Quick Links

OrCAD X—Freedom to design boldly

Unlock the Future with OrCAD X: PCB Design Simplified

Announcements

News, FAQs, and related info about how to best use the community.

Application Support and Knowledge Portal

Cadence Online Support puts the help you need within easy reach – around the clock, seven days a week

Training

Cadence helps you get the most out of your investment in our technologies through a wide range of education offerings.

Why Join?

  • Ask questions and get answers from Cadence experts
  • Share your expertise and learn from other Cadence users' experiences
  • Participate in technology- and solution-focused discussions
  • Leaderboard

    • 1
      Rita Fung
      Rita Fung 76 Points
    • 2
      AVAQ Semi
      AVAQ Semi 65 Points
    • 3
      ST202606301857
      ST202606301857 50 Points
    • 4
      EDA Star
      EDA Star 41 Points
    • 5
      KS202606109251
      KS202606109251 40 Points
  • Leaderboard

    • 1
      steve
      steve 17,884 Points
    • 2
      oldmouldy
      oldmouldy 13,840 Points
    • 3
      eDave
      eDave 10,381 Points
    • 4
      ShawnLogan
      ShawnLogan 9,725 Points
    • 5
      skillUser
      skillUser 7,518 Points
CDNS - feedback

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

Latest Posts

  • Discussion

    Remove CIS 16.5 "Start Page"

    Category: PCB Design

    By dschaefer

    •

    updated over 14 years ago by Ejlersen

    3 replies • 2057 views
  • Discussion

    Design rule to support mass production

    Category: PCB Design

    By C Shiva

    •

    updated over 14 years ago by C Shiva

    2 replies • 14218 views
  • Discussion

    newbie SKILL question: how to create a via

    Category: Custom IC SKILL

    By chrisgregg

    •

    updated over 14 years ago by blankman

    6 replies • 21292 views
  • Discussion

    About unregular shape in layout: Cadence CAD and fabrication

    Category: Custom IC Design

    By bjbit

    •

    updated over 14 years ago by bjbit

    2 replies • 14930 views
  • Discussion

    optimization in ADE GXL

    Category: Custom IC SKILL

    By ranran

    •

    updated over 14 years ago by ranran

    1 replies • 15380 views
  • Discussion

    Power Breakdown (sequential, combinational, I/O) report for hierarichal design

    Category: Digital Implementation

    By AliShami

    •

    started over 14 years ago

    0 replies • 924 views
  • Discussion

    Assura 3.1.4 LVS error

    Category: Hardware/Software Co-Development, Verification and Integration

    By stefanobre

    •

    updated over 14 years ago by stefanobre

    1 replies • 15270 views
  • Discussion

    Turning off Spectre Views

    Category: Custom IC Design

    By JustinTaylor86

    •

    updated over 14 years ago by JustinTaylor86

    2 replies • 14807 views
  • Discussion

    gdb debugging a Systemverilog DPI (shared library) that is run from ncsim

    Category: Functional Verification

    By cubicle82

    •

    updated over 14 years ago by ravi999

    2 replies • 18863 views
  • Discussion

    about the CSHRC

    Category: Custom IC SKILL

    By Vi Muthukumar

    •

    updated over 14 years ago by Andrew Beckett

    1 replies • 15403 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information