Custom IC Design

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Discussion

How to disable those envSetVal warnings when calling ocean scripts?

Category: Custom IC Design

By Alex Liao

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updated over 9 years ago by Andrew Beckett

5 replies • 15948 views
Discussion

expression to get a scalar after a sweep

Category: Custom IC Design

By davidzti

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updated over 9 years ago by davidzti

8 replies • 20871 views
Discussion

transient simulation convergence cadence : fully differential sample and hold

Category: Custom IC Design

By imagepix

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updated over 9 years ago by Andrew Beckett

1 replies • 17892 views
Discussion

two dimensional bus notation in schematics

Category: Custom IC Design

By mheshami

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updated over 9 years ago by Andrew Beckett

7 replies • 22075 views
Discussion

Random variable for each corner in ADE-XL

Category: Custom IC Design

By Johanny Saenz

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started over 9 years ago

0 replies • 13764 views
Discussion

file sorting order in library manager

Category: Custom IC Design

By olalivier

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updated over 9 years ago by Andrew Beckett

3 replies • 14767 views
Discussion

Cadence Virtuoso Memory Limitation Issue

Category: Custom IC Design

By jdp721

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updated over 9 years ago by jdp721

2 replies • 19619 views
Discussion

What is a display packet

Category: Custom IC Design

By greenmax

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updated over 9 years ago by Andrew Beckett

1 replies • 16197 views
Discussion

inconsistency while measuring sub-threshold currents.

Category: Custom IC Design

By geovol

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updated over 9 years ago by Andrew Beckett

5 replies • 16732 views
Discussion

Ruler setting

Category: Custom IC Design

By Julien Terrier

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updated over 9 years ago by Julien Terrier

3 replies • 15912 views
Discussion

ADE XL - Save Netlist in different location from results

Category: Custom IC Design

By Michele Ancis

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updated over 9 years ago by Michele Ancis

4 replies • 1927 views
Discussion

How can I create synchronized clones?

Category: Custom IC Design

By 213kkw

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updated over 9 years ago by 213kkw

4 replies • 16749 views
Discussion

ADEXL results list ordering

Category: Custom IC Design

By PNadeau

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updated over 9 years ago by PNadeau

2 replies • 16136 views
Discussion

Is there a way to exclude parasitic capacitances of a MOS in BSIM model?

Category: Custom IC Design

By BaaB

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updated over 9 years ago by Andrew Beckett

3 replies • 14647 views
Discussion

Cadence Virtuoso automatic routing wire width consideration

Category: Custom IC Design

By Mamad

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updated over 9 years ago by Mamad

3 replies • 15651 views

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