Custom IC Design

Latest Posts

Discussion

adexl's "Run Simulation" always hidden when first open

Category: Custom IC Design

By dogman4
•
updated 2 months ago by dogman4

3 replies • 418 views
Discussion

Function to Detect Minimum Pulse Width

Category: Custom IC Design

By Kevin T Buck
•
updated 2 months ago by Kevin T Buck

1 replies • 775 views
Discussion

Problem with Liberate and Verilog-A Model

Category: Custom IC Design

By FM202408077836
•
updated 2 months ago by FM202408077836

2 replies • 1204 views
Discussion

Layout: Edit-in Place -> show full layer palette

Category: Custom IC Design

By PK202501238151
•
updated 2 months ago by PK202501238151

2 replies • 449 views
Discussion

Wprobe - Power/PAE calculation in Envelope Wireless analysis

Category: Custom IC Design

By UbltSR
•
started 2 months ago

0 replies • 228 views
Discussion

Library Manager: Can it support e.g. bitmap pictures and libre office documents?

Category: Custom IC Design

By StephanWeber
•
updated 2 months ago by henker

1 replies • 853 views
Discussion

How to define Cell based on S-Parameters

Category: Custom IC Design

By spatz
•
updated 2 months ago by Saloni Chhabra

3 replies • 1073 views
Discussion

View list and Stop list in Cadence PVS

Category: Custom IC Design

By thiruvenkata
•
updated 2 months ago by ilyaF

4 replies • 1318 views
Discussion

Hierarchical LVS Issues or how to deal with LVS hierarchy

Category: Custom IC Design

By spatz
•
updated 2 months ago by RobMan

3 replies • 1171 views
Discussion

Different PSS and Pnoise result with different Fund and sample_ratio settings

Category: Custom IC Design

By YutaoLiu
•
started 3 months ago

0 replies • 827 views
Discussion

The tran+stb simulation phase curve declines from -150 degree

Category: Custom IC Design

By liangqunshan
•
updated 3 months ago by liangqunshan

1 replies • 399 views
Discussion

Check and Asserts in Monte-Carlo

Category: Custom IC Design

By lagoud
•
updated 3 months ago by KV202505288952

5 replies • 2102 views
Discussion

"DrgEnb" of techDisplays class in Virtuoso Techfile IC5.1 & IC6.1

Category: Custom IC Design

By MC202505188948
•
updated 3 months ago by Andrew Beckett

1 replies • 315 views
Discussion

2D Sweep in Spectre Netlist

Category: Custom IC Design

By KC202505278026
•
updated 3 months ago by KC202505278026

2 replies • 1078 views
Discussion

Cadence LVS Error in the Schematic vs Layout

Category: Custom IC Design

By ranaya
•
updated 3 months ago by ranaya

2 replies • 1153 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.