Custom IC Design

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Discussion

DRC check and LVS check has no error but still seeing the layer error?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Andrew Beckett

1 replies • 6458 views
Discussion

Setting dynamic parmeter in pss analysis

Category: Custom IC Design

By Abhrarup

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updated over 2 years ago by Andrew Beckett

1 replies • 6556 views
Discussion

Maestro : Width of columns in "Results" Tab is large. How to reduce it?

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 1558 views
Discussion

Maestro: Simulation Settings as Output Expressions

Category: Custom IC Design

By Saikiran IND

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updated over 2 years ago by Saikiran IND

2 replies • 7163 views
Discussion

The region of operation of MOS transistor

Category: Custom IC Design

By PhD Student

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updated over 2 years ago by PhD Student

12 replies • 14182 views
Discussion

Simulation startup is too slow

Category: Custom IC Design

By Firdos

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updated over 2 years ago by ShawnLogan

1 replies • 6945 views
Discussion

rexMatchp error when netlist

Category: Custom IC Design

By sjwprcker

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updated over 2 years ago by Andrew Beckett

1 replies • 6925 views
Discussion

Ramp signal generator in Verilog-A

Category: Custom IC Design

By delgsy

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updated over 2 years ago by ShawnLogan

1 replies • 9800 views
Discussion

Post Trimming Simulation for Oscillator Circuit

Category: Custom IC Design

By yoshi777

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updated over 2 years ago by ShawnLogan

8 replies • 11216 views
Discussion

design/global variables import from veilogA

Category: Custom IC Design

By Majco

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started over 2 years ago

0 replies • 857 views
Discussion

Pixelate Custom Curved Polygon According to Grid in Virtuoso Layout Suite L

Category: Custom IC Design

By Herramar

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updated over 2 years ago by Andrew Beckett

3 replies • 7554 views
Discussion

Unexpected capacitor values in the av_extracted view file output?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

6 replies • 8436 views
Discussion

How to compare the before and after extraction values of resistance and capacitance?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

8 replies • 8671 views
Discussion

Title Block cell issue

Category: Custom IC Design

By Larry Allen

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updated over 2 years ago by Andrew Beckett

6 replies • 7523 views
Discussion

Importance of "Enable CellView Check" while filling the quantus assura extraction form?

Category: Custom IC Design

By Vishesh Gupta

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updated over 2 years ago by Vishesh Gupta

2 replies • 1372 views

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